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verilog全数字锁相环pll
- verilog全数字锁相环，用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
pllverilog 完成pll锁相环的设计
- 基于FPGA的程序编写，完成pll锁相环的设计，实验证明次程序是完整的-FPGA-based programming, complete pll PLL design, experiments show that second program is complete
pll.rar
- 模拟锁相环（apll）的一些simulink模型,Analog phase-locked loop (apll) some simulink model
PLL
- simulink 仿真锁相环的一个pdf-a pdf of pll using simulink
PLL
- matlab中锁相环（PLL）的仿真...功能完好-matlab in the phase-locked loop (PLL) simulation function well ...
costas_loop
- 使用改进的COSTAS环实现锁相环（PLL），应用于高动态的数字化接收系统-COSTAS Central improved to achieve phase-locked loop (PLL), used in high dynamic digital reception system
fq_div
- pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
pll
- 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
PLL
- 可以实现自动锁相环功能的C源程序代码模块，-Can be achieved automatically PLL function C source code modules,
pll
- 关于数字锁相环方面的代码,觉得还可以，或许对大家有用-the code of the pll
PLL
- 基于matlab的锁相环（PLL）仿真源代码-Matlab based on the phase-locked loop (PLL) simulation source code
pll
- 设计的软件锁相环的例子，自己写的，根据原理编的-PLL design example of software that he wrote, according to the principle for the
pll-matlab
- 通信常用锁相环仿真－matlab格式－有简单注释。-Communications Common PLL simulation-matlab format- a simple comment.
PLL
- 利用锁相环，比较好的实现了载波同步-PLL
pll
- 用matlab模拟仿真锁相环，一个很好的程序，希望能帮到你-PLL with matlab simulation, a very good program, hope you can help
PLL
- 通过对输入时钟进行锁相环IP核配置，产生所需的时钟信号(By configuring the input clock PLL, the IP core generates the desired clock signal)
PLL_simulink
- pll锁相环simulink模型，通俗易懂，可以实现的模型(Pll phase locked loop simulink model, easy to understand, can achieve the model)
并网逆变器的程序电流环控制并有DA以及锁相部分
- 光伏逆变锁相环，使用DSP28335，实现频率跟踪，首先采样，然后PI，然后输出(Photovoltaic inverter PLL, using DSP28335, to achieve frequency tracking, first sampling, then PI, and then output)
并网逆变器中全软件锁相环的设计与实现
- 讲述并网逆变器中全软件锁相环的设计与实现，，即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环（双dq–PLL），完全消除了检测误差传统的同步参考框架（SRF–锁相环PLL）(and implementation of all software phase-locked loop in grid connected inverter is described, that is, detecting the positive a
PLL（锁相环）_TEST_OK
- 通过STM32程序的编写来形成闭环锁相环，锁住波形的稳定，保持系统的稳定。(Through the preparation of STM32 program to form a closed-loop phase-locked loop, lock waveform stability, maintain the stability of the system)