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标准sdr sdrAM控制器参考设计_verilog_lattice
- 标准sdr sdrAM控制器参考设计，Lattice提供的verilog源代码-standard sdr sdrAM controller reference design, the Lattice Verilog source code
ref-sdr-sdram-vhdl
- 标准sdr sdrAM控制器参考设计_verilog_lattice\\sdr_ctrl.v
sdr
- 软件无线电sdr实现GPS的代码,软件无线电sdr实现GPS的代码
sdr-sdrAM-vhdl
- sdr-sdrAM-vhdl单个sdrAM的控制，通过它可以学习了解sdrAM的时序等，很有帮助哦 ！
verilog 128位 突发4. sdr fpga控制器
- verilog 128位 突发4. sdr fpga控制器,verilog 128 bit unexpected 4. sdr fpga controller
HY57V641620HG.vp.rar
- Hynix公司8M Byte sdr sdrAM的Verilog语言仿真实现,Hynix' s 8M Byte sdr sdrAM Simulation of the Verilog language
eth_send
- 清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。-Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.
sdr
- 直接序列扩频通信的Verilog仿真代码，在Quartus II中实现。-Direct sequence spread spectrum communication Verilog simulation code, implemented in Quartus II.
gps-sdr
- C++ 开发的GPS软件接收机，支持硬件为USRP， 目前只支持GPS L1 c/a码信号接收-A software GPS receiver developed with C++ .The Surport hardware is USRP. Now it can reveive and process the GPS L1 C/A signal.
sdr_matlab
- 多通道软件化软件无线电发射机实现程序,采样速率为25KHz，基于多相滤波的8通道发射机源程序。-Multi-channel sdr(soft defined radio)
sdr-sdrAM-ctl1
- sdr sdrAM控制器，FPGA vhdl代码-sdr sdrAM Controller
ref-sdr-sdram-verilog
- sdrAM的vegilog代码，做一个sdrAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-sdrAM
ref-sdr-sdram-verilog
- 标准SRD sdrAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD sdrAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
ref-sdr-sdram-vhdl
- 基于VHDL编写的sdr-sdrAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the sdr-sdrAM controller programming, is now commonly used in industry RAM controller
sdr
- Its a simple sdr to change modulation schemes
sdr
- FPGA based implementation of a sdr - codes in Verilog HDL for the processor and control.-FPGA based implementation of a sdr- codes in Verilog HDL for the processor and control.
gps-sdr-gps-sdr-271efd1
- The GPS-sdr is a highly modular, multithreaded enabled, C++ application. The software is a GPS L1 C/A code receiver with a fast acquisition/weak signal capability.
sdr-sdram-(verilog)
- Altera的sdr sdrAM模型，verilog实现，带说明书文件以及仿真文件、sdrAM原型文件。-Altera' s sdr sdrAM model, verilog implementation, with manual files and simulation files, sdrAM prototype file.
标准sdr sdrAM控制器参考设计，Lattice提供
- 说明： sdr sdrAM 控制器 来自lattice 已经分析代码可用!大家可以参考修改，形成自己的实例(Descr iption: sdr sdrAM controller from lattice has been analyzed code available, we can refer to modify, to form their own examples)
gnss sdr
- Gnss sdr details in c and c++