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uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
FPGA-RS232-verilog
- fpga上的串口驱动程序，包括接收主机来的数据（deserial）和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug deb
UART
- 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
UART
- 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
fpga_uartrw
- FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
UART_DESIGN
- The use of hardware descr iption languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level descr iption not only increases design productivity, but also provides unique advantages for design verif
xapp341
- verilog uart for spartan 3 fpga, its great
uart
- fpga 串行口 接收和发送程序，采用verilong语言编写-fpga uart ，receive and send include writed by verilog language
UART
- Verilog HDL写的实现ＵＡＲＴ收发程序-Realization of Verilog HDL UART receive written procedures
UART
- xilinx官网提供的VHDL,UART串行通信模块，肯定好用，官方提供-xilinx official website provides VHDL, UART, FPGA communication module is certainly easy to use, official
Uart
- fpga verilog语言，写的串口通讯，经测试完全没有问题-fpga verilog uart communication
UART-Altera
- 使用Atera FPGA CycloneII 实现串口通信，遵循RS232协议。FPGA上的模块实现了数据的接收，取补码和发送。(Achieve serial communication with FPGA, following the protocol of RS232.)
uart
- UART 功能模块，Verilog，简单实用(UART function module, Verilog, simple and practical)
uart
- UART的串口程序，收发功能都已实现，直接可用(UART serial procedures, transceiver functions have been achieved, directly available)
UART-master
- FPGA Based UART in Verilog
uart
- FPGA Verilog设计UART通讯程序(UART communication code with Verilog in FPGA)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
VerilogUart_Modelsim
- 使用Verilog编写的UART ，用Modelsim仿真工程。(use Verilog Write UART Program, Modelsim simmulate the project)
uart
- 电脑端发送数据与FPGA接收数据程序，uart模块，以及一部分项目里包含的其他的程序(Program for sending data from computer and receiving data by FPGA, UART module)