搜索资源列表
spider_v1.2
- 网络蜘蛛1.3版, 功能变更： 1． 关于对处理过URL和待处理URL的存储检索。 利用文件系统存储这些信息，利用Hash碰撞分页算法，加上最新数据的内存缓存，实现高效的信息检索。平均检索的效率0.01s 2． 修改前面版本URL替换产生的中文问题。 -network spider version 1.3, the functional changes : 1. On the right URL and processed pending the URL stora
Keil_C_for_AT45DB041
- 提供DataFlash（AT45DB041）的底层读写驱动函数，包括内存读写，缓存读写，内存与缓存之间的数据交换等等。-provide DataFlash (AT45DB041) literacy drive the bottom function, memory read and write, read and write cache, and cache memory for data exchange between and so on.
Cache_FIFO
- 模拟内存高速缓存技术C源码，主要是FIFO形式。-simulated high-speed cache memory technology C source code, is the main form of FIFO.
EE271v01
- Using Cache Memory on lackfin Processors
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
DHRY
- The DHRY program performs the dhrystone benchmarks on the 8051. Dhrystone is a general-performance benchmark test originally developed by Reinhold Weicker in 1984. This benchmark is used to measure and compare the performance of different
AT45DB041B-c51pdf
- SPI接口4M位高速存储芯片，带2*512缓存-SPI interface 4M-bit high-speed memory chips, with 2* 512 cache
cache
- 实现LRU算法的Cache源代码，可以用来支持整个系统中某种对象数量的个数限制，同时，通过LRU算法保证使用频度高的对象尽可能的驻留内存。 该算法可以用来支持J2EE系统性能提升，同时又可以控制内存安全使用。-LRU algorithm implementation Cache source code, can be used to support the system as a whole number of objects in a certain number of restricti
Cache_dotnet_cs
- 实现LRU算法的cache dotnet C#源码，用来支持asp.net程序提升系统访问速度。同时保证系统能够控制内存的使用不产生泄漏。-LRU algorithm implementation cache dotnet C# source code, used to support asp.net procedures to enhance the speed of system access. At the same time to ensure that the system be ab
cache
- OSCACHE API 供开发内存共享查阅使用。-OSCACHE API for shared memory access to the use of the development.
CACHE
- 一个arm7开发板上cathe内存测试程序，该程序用c语言编写。-a arm7 Development Board cathe memory test program, the program is available c language.
P6_Cache
- MEMORY CACHE SIMPLE CODE
cache
- This a paper that is good for someone who wants to design Cache memory.-This is a paper that is good for someone who wants to design Cache memory.
Memory
- Memory Hierarchy in Cache-Based System
cache
- cache设计，直接映射，回写式cache。256行，每行四字。 ram按字存储，大小为64K字。-cache design, direct mapped, write-back cache. 256 lines of four characters. ram memory by the word, the word size is 64K.
cache
- cache n. 高速缓冲存储器 一种特殊的存储器子系统，其中复制了频繁使用的数据以利于快速访问。存储器的高速缓冲存储器存储了频繁访问的 RAM 位置的内容及这些数据项的存储地址。当处理器引用存储器中的某地址时，高速缓冲存储器便检查是否存有该地址。如果存有该地址，则将数据返回处理器；如果没有保存该地址，则进行常规的存储器访问。因为高速缓冲存储器总是比主RAM 存储器速度快，所以当 RAM 的访问速度低于微处理器的速度时，常使用高速缓冲存储器。-cache n. a special cache m
Embedded-memory-for-logic-chips
- 对于逻辑芯片的嵌入存储器来说，嵌入式SRAM 是最常用的一种，其典型的应用包括片上缓冲器、高速缓冲存储器、寄存器堆等-Embedded memory for logic chips, the embedded SRAM is the most common one, its typical applications include on-chip buffers, cache memory, register, etc.
CCacheManager
- cachemanager, to clear n maintain cache memory
cache
- 缓存基础，对各种缓存的介绍，包括浏览器缓存，cpu缓存，内存缓存，磁盘缓存等。-Cache based on the introduction of various caches, including browser cache, cpu cache, memory cache, disk caching.
basic-cache
- Verilog codes for cache memory with direct mapping and write back policy.