当前位置：
首页 资源下载
搜索资源 - clock FPGA Verilog
搜索资源列表
-
0下载：
1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器，使其能够支持基本的指令。
2. 用Verilog HDL实现单时钟CPU控制器，在ISE上进行波形仿真，并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-
-
-
0下载：
基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。
使用计时器的方式产生时钟波形。
提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
-
-
3下载：
使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
-
-
0下载：
xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
-
-
0下载：
用verilog实现的数字跑表，下载到FPGA开发板上验证通过。下载后从新分配引脚即可用。-Verilog implementation using digital stopwatch, download to FPGA development board to verify the adoption. After the download you can use the new distribution of pins.
-
-
0下载：
多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
-
-
0下载：
clock divider for fpga in verilog and vhdl
it contains
counter.vhd
clock1.v
clock_divider.doc-clock divider for fpga in verilog and vhdl
it contains
counter.vhd
clock1.v
clock_divider.doc
-
-
0下载：
实现多功能电子表，含有闹铃，时间精确到毫秒-Achieve multi-functional electronic watch, with alarm, time, milliseconds
-
-
0下载：
verilog adc0809控制器FPGA实现，编译通过，系统时钟分频，满足ADC时钟要求。-verilog adc0809 controller FPGA, compiler, system clock frequency to meet the requirements of ADC clock.
-
-
0下载：
verilog设计的计时表，数字电路设计，FPGA-using verilog design watch, digital circuit design, FPGA
-
-
0下载：
FPGAverilog数字时钟,基于quartal ii 下的数字时钟电路程序-FPGA verilog digital clock
-
-
0下载：
fpga verilog 2位数码管显示仿真及说明-fpga verilog 2 digit LED display and descr iption of the simulation
-
-
0下载：
FPGA编程，用Verilog语言实现数字钟功能-The FPGA programming, the function for digital clock with Verilog language
-
-
0下载：
基于FPGA实现数码管数字时钟功能
使用芯片为EP2C8Q208C8N,使用数码管显示数字时钟，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。-Based on FPGA digital tube digital clock function uses chip EP2C8Q208C8N, use digital display digital clock, using Verilog language programming, the present exam
-
-
0下载：
教程
基于FPGA的智能闹钟，控制NOKIA5110(Intelligent alarm clock based on FPGA, control N O K I A 5110)
-
-
0下载：
实现奇数、偶数分频,fpga,Verilog,时钟分频(clock divider,frequency division)
-
-
0下载：
采用verilog语言，实现时钟信号的7分频(Realize the 7 frequency division of the clock signal)
-
-
0下载：
veilog程序可以在fpga上完成数字钟程序(Verilog program can be completed on the digital clock fpga procedures)
-
-
1下载：
自己开发的电子时钟小程序，通过数码管显示时间，key1和key2控制校时校分，key3切换时钟模式和闹钟模式，切换到闹钟模式再按key1和key2即可设定闹钟时间。key4控制开启/关闭闹钟。有整点报时功能。(Self developed electronic clock applet, through the digital tube display time, key1 and key2 control time correction, Key3 switch clock mode and
-
-
0下载：
基于Basys2的带测温、定闹钟、温度上下限报警装置的数字电子钟，可自动处理闰年闰月。(Basys2 temperature measurement, alarm clock, temperature alarm device based on digital electronic clock, can automatically handle leap year leap.)
-
