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TestAsm1
- VC裡面內嵌組合語言 能將組合語言的優點寫在C語言裡面-Inline combinational language in VC. Can build the merit of combinational language in C .
vhdl程序例子
- vhdl程序源代码，包括Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等-VHDL source code, including Combinational Logic Counters Shift Registers State Machines Registers Memory S
LogicGate
- 1. 用面向对象思想描述组合电路； 2. 对给出的输入，计算输出。要求编程实现（C＋＋语言），打印运行结果。 -1. Using object-oriented descr iption of combinational circuit; 2. For a given input, output calculation. Demand programming (C + + language), Print operating results.
sgsim
- 代码名称：组合逻辑电路仿真器 代码说明：组合逻辑电路仿真器 工具/平台：VC++ 作者：上官晨寰 邮件地址：sgch1982@163.com-code name : combinational logic circuit simulator code : combinational logic circuit simulator tools / platform : VC Author : Shangguan morning atlanto-mail ad
Shifters_vhdl
- -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at --- Title : Barrel Shift
PLDsheji
- 含有：多时钟系统设计，如何处理建立保持时间，如何处理内部三态电路，消除组合逻辑产生的毛刺，用单片机配置fpga-contain : multi-clock system design, how to deal with the establishment and maintenance of the time, how to handle the internal three-state circuit, Elimination of the combinational logic Burr,
VHDL 语言例程集锦
- 包括很多有用的VHDL源代码，如下。文件为PDF格式，可以直接copy你想要的部分，然后粘贴到你自己的VHDL文件中。能帮你节省很多开发时间。 1.Combinational Logic 2.Counters 3.Shift Registers 4.Memory 5.State Machines 6.Registers 7.Systems 8.ADC and DAC 9.Arithmetic
Div3
- 一个除3器的Verilog源码，用于视频解码器的熵解码部分。纯组合逻辑，大小和加法器差不多。-In addition to device a Verilog source code 3, the video decoder for entropy decoding part. Pure combinational logic, about the size and adder.
immediate_divide_module
- 用组合逻辑实现循环除法器。稳定、安全、可靠。-Combinational logic loop divider. Stable, secure, and reliable.
100exampleofvhdl
- 100个VHDL例子，包括各种逻辑门、组合逻辑电路及时序电路-100 VHDL examples, including a variety of logic gates, combinational logic circuit and timing circuit
yima3_8
- 译码是编码的逆过程，它的功能是将具有特定含义的二进制码进行辨别，并转换成控制信号。此程序虽然简单，但能很好的理解用eril HDL语言设计组合逻辑电路的过程。-Decoding is the inverse process of encoding, and its function is to have a specific meaning to distinguish between binary code and converted into control signals. Althoug
mux
- 多路选择器是一个多输入，单输出的组合逻辑电路，在算法电路的实现中常用来根据地址码来调度数据。-MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.
CoursewareOfDigitalCircuit
- 这是关于数字电路的ppt课件，对于组合逻辑电路和时序逻辑电路都讲得比较清晰透彻。-This is on digital circuits ppt courseware, for combinational logic circuits and sequential logic circuits have stood out clear and thorough.
shuzidianzizhong
- 此次设计与制做数字钟就是为了了解数字钟的原理，从而学会制作数字钟.而且通过数字钟的制作进一步的了解各种在制作中用到的中小规模集成电路的作用及实用方法.且由于数字钟包括组合逻辑电路和时叙电路.通过它可以进一步学习与掌握各种组合逻辑电路与时序电路的原理与使用方法.-Design and production of the digital clock digital clock in order to understand the principle, so learn to create digit
DigitalLogic
- 组合逻辑电路、时序逻辑电路及数字逻辑电路系统的设计、安装、测试方法-Combinational logic circuits, sequential logic circuits and digital logic circuit system design, installation, testing methods
the-combinational-logic-circuit
- 关于组合逻辑电路的知识，很好的资料，很全-Knowledge of the combinational logic circuit
Combinational-logic-circuit
- fpga verilog 组合逻辑电路代码仿真及说明-fpga verilog combinational logic circuit simulation code and descr iption
Combinational
- this is a sample of combinational circuit in Verilog and VHDL. such as multiplexer, decoder, adder etc
SV-Combinational-Logic
- system Verilog combinational logic
L5 - Combinational Logic Design with Verilog
- combinational circuits