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32 bit up/down counter with count enable based on altera fpga
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介绍一种软件实现分频器和32位计数器，采用可编程逻辑芯片，运用verilog语言设计出一种分频器和32位计数器 -Introduce a software implementation of divider and 32-bit counter, using programmable logic chips, using verilog language to design a divider and 32-bit counter
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Verilog HDL语言编写的32位程序计数器（PC）完整工程及相应仿真，QuartusII7.2下编译通过可正常使用。-Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.
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FPGA开发板做的一个简单LED驱动，使用Verilog语言实现- This is an example of a simple 32 bit up-counter called simple_counter.v
It has a single clock input and a 32-bit output port
module simple_count(input clock , output end of module counter
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Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
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