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vcpwmcpldcar
- vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码
LCED12864DRV
- 是128*64程序，也是现在用的最多的，是CPLD上面用的
add128
- 128位的地址译码器，在cpld或者fpga上实现兼可-128-bit address decoder, in the CPLD or FPGA implementation and may
FPGA_Verilog_LCD_12864
- 使用Verilog HDL语言编写的驱动LCD12864的时序，可以直接用FPGA/CPLD驱动LCD12864了。-Using Verilog HDL language driver LCD12864 timing, can be directly used FPGA/CPLD driver LCD12864 the.
EPM240ZT100
- The MAX II CPLD has the following features: ■ Low-cost, low-power CPLD ■ Instant-on, non-volatile architecture ■ Standby current as low as 29 μA ■ Provides fast propagation delay and clock-to-output times ■ Provides four global clocks with
uart_verilog
- The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This
uart_vhdl
- The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This
add128
- 128位的地址译码器，在cpld或者fpga上实现兼可-128-bit address decoder, in the CPLD or FPGA implementation and may