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FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
verilogfenpinqi
- verilog分频器代码 分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
dividerverilogdesign
- verilog 分频器设计 偶数分频器和奇数分频器-divider verilog design even and odd divider divider
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
begin
- 9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述：-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code:
VerilogHDL
- 9/7提升小波变换中奇偶分裂步、预测步、边界延拓处理和模块测试平台的Verilog代码描述：-9/7 lifting wavelet transform in odd and even split-step, prediction step, boundary extension process and module test platform described in Verilog code:
ANNA-Y
- 此源程序可包含verilog与vhdl任意倍数的分频，奇数偶数分频均可，均已通过验证，可直接使用。-The source code can contain multiple verilog and vhdl any frequency, both odd and even frequency, are validated and can be used directly.
div_frequency
- 任意分频器，用Verilog HDL实现，只需修改参数可以实现奇数、偶数分频，FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
division-verilog
- 文章详解介绍了用Verilog HDL语言编写任意倍偶数分频和奇数分频的原理以及源程序，都通过仿真，结果完全正确。-The article introduced with sep Verilog HDL language writing any times frequency and the odd points even points of the principle and the frequency source program, through the simulation, the r
verilog--divide-programs
- verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
clkdiv
- 任意分频电路的verilog实现，包含奇分频和偶分频-Arbitrary divider circuit verilog achieve, contains odd and even frequency divider
VerilogFreq-div
- Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法-Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide
fenpinjishuqi
- 本文档包括实现分频的方法以及奇数分频偶数分频的verilog代码 经测试可用-This document includes methods to achieve divide and even the odd divider divider verilog code used by the test
fenpin
- 用verilog HDL编写的任意数分频，包括偶数分频和奇数分频等。-The any number of points, including even frequency and odd frequency, etc..using Verilog HDL
Divider_Verilog_ISE
- 用Verilog语言编写的分频程序，包含奇数分频、偶数分频等许多例程。-Using Verilog language division procedures, including odd division, even dividing and many other routines.
fenpin
- 任意分频VERILOG实现，包括奇数分频、偶数分频，与小数分频等等。-Arbitrary frequency VERILOG implementation, including the odd frequency, even frequency, and fractional frequency division, etc..