搜索资源列表
UART.使用FPGA的fifo，状态机
- 使用FPGA的fifo，状态机，乒乓操作等实现了异步UART。,The use of FPGA-fifo, state machine, ping-pong operation to achieve the asynchronous UART.
fifo
- 先进先出存储电路fifo，实现队列存储结构-xianjin xianchu chunchu dianlu fifo
fifo_Design
- 一种基于格雷码的异步fifo设计与实现,8*8位的fifo vhdl 源码-Gray-code based on the Asynchronous fifo Design and Implementation
fifo
- 异步fifo的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous fifo can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
fifo
- 此程序为存储器常用的fifo（先入先出），程序中没有指明位宽，这样更适合于初学者进行套用-This process commonly used for the memory fifo (fifo), the procedure is not specified bit, so more suitable for beginners to apply
fifo
- 一个fifo设计的例子，例子简单，但很经典。 是学好数字设计的好开端。-A fifo design examples, example of simple, but very classic. Learn digital design is a good start.
fifo
- 利用一个SAM设计一个fifo 的存储器-SAM uses a design of a fifo memory
fifo
- 一个fifo源代码，基于Altera FPGA-A fifo source code, based on Altera FPGA
fifo
- 一个用vhdl源码编写的先进先出(fifo)缓冲器模块.可以进行fifo的仿真验证-A source prepared by vhdl fifo (fifo) buffer module. Can verify fifo simulation
vhdlfi
- fifo vhdl源码，高可靠性，带有格雷码同步，有需要可依进行参考！-fifo vhdl source, high reliability, with Gray-code synchronization, there is a need-based reference!
fifo
- fifo example vhdl code
fifo
- fifo中文应用笔记，对学习单片机RAM、大量数据处理很有帮助。-fifo notes
fifo
- it is a verilog code written for fifo in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
fpga.fifo
- 异步fifo是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步fifo采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous fifo is an important module which always used to absorb the
fifo-interface
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
fifo
- 512×8bid的fifo 含工程文件，基于QUARTUs-512 × 8bid the fifo with the project document, based on the QUARTUsII
fifo
- This code is a fifo memory vhdl developed in ISE Software
fifo
- 完整的fifo完整源代码，通过仿真 完整的fifo完整源代码，通过仿真 -Complete fifo full source code, through the simulation of the complete fifo full source code, through the simulation of
fifo
- 同步fifo 创建一个256x8大小的同步fifo，并通过串口发送数据初始化fifo，FPGA内部读取fifo的数据通过窗口发送到PC-fifo
fifo
- 同步和异步fifo，vhdl实现。希望对大家有所帮助。-Synchronous and asynchronous fifo, vhdl implementation. We want to help.