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关于h.264视频解码器完全源码（verilog）-With regard to h.264 video decoder full source code (verilog)
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H.264解码器，用verilog写成，可以在FPGA上实现baseline的264解码-H.264 decoder, written with verilog, can be achieved in the FPGA on the baseline of 264 decoding
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H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块-Standard H.264 decoder all verilog source, including intra-, inter-frame, transform coding, entropy coding, filtering all modules
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h.264(verilog HDL)
这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
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H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块和著名的6502的软件源码-The standard H.264 decoder all verilog source code, including the frame, frame, transform coding, entropy coding, filtering all modules and the famous 6502' s software source code
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VERILOG source code of a H.264 baseline decoder.
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MPEG-4/AVC - H.264 CABAC decoder written in VHDL and synthesis on a Virtex 5
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h.264完整的解码器，用verilog实现，属于opencores-h.264 full decoder, implemented by verilog, one of opencores
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H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
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