目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理,At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA

MII接口编程,用于收发以太网MAC帧的FPGA实现。-MII interface programming, send and receive Ethernet MAC frame for the FPGA.

用FPGA实现MII的数据传送时序控制,方法简单实用，设计及其精巧-implementation of MII data transmission’s timing control

以太网控制器源码，verilog语言,包含MAC、MII接口-Ethernet controller ,include MAC and MII interfaces ,by verilog

以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design