当前位置：
首页 资源下载
搜索资源 - serial parallel VHDL
搜索资源列表
-
0下载：
该模块主要完成并串转换功能。其中system_clk是输入并行时钟的频率，它是串行时钟serial_clk的八倍。byte_data_en是输入并行数据使能信号，byte_data是输入并行数据。serial_data是转换后的串行数据，bit_data_enable是串行数据有效信号。,The module main is completed and the string conversion functions. System_clk which is an input parallel c
-
-
0下载：
一种基于状态机设计的串并行转换电路，将LTC1196(ADC)的串行输出数据转换成并行数据的转换电路， ADC的时钟由转换电路提供，,Design a state machine based on parallel conversion circuit of the series will be LTC1196 (ADC) output of the serial data into parallel data conversion circuit, ADC clock provided by
-
-
0下载：
并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
-
-
0下载：
串行输入并行输出 用vhdl语言描述的 有源代码主打色,Serial input parallel output using vhdl language to describe the main color of the source code
-
-
1下载：
用VHDL语言将并行的8位数据换成串行输出-The parallel 8 is the data replaced with the serial output
-
-
1下载：
Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel
conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a
simplified UTMI interface. Currently doesn t do any error checking in
the RX section [should probably check f
-
-
1下载：
这个是我花了一个星期的CRC算法，有并行与串行的区别与时序的分析。。。。希望站长能够同意-This is a week I spent the CRC algorithm, there is the difference between parallel and serial and timing analysis. . . . Hope that regulators can not agree
-
-
0下载：
三线spi接口，用verilog实现，作为一个模块，可以接收并行数据，然后串行发送-Three Line spi interface, using Verilog implementation, as a module, can receive parallel data, and then send the serial
-
-
0下载：
由于计算机中大部分器件使用的是串行，本程序实现了数字电路中常用的串行输入并行输出的功能。-Because most of the computer using a serial device, the program realization of digital circuits used in serial input parallel output function.
-
-
0下载：
串口通信的概念非常简单，串口按位（bit）发送和接收字节。尽管比按字节（byte）的并行通信慢，但是串口可以在使用一根线发送数据的同时用另一根线接收数据。它很简单并且能够实现远距离通信。比如IEEE488定义并行通行状态时，规定设备线总常不得超过20米，并且任意两个设备间的长度不得超过2米；而对于串口而言，长度可达1200米。典型地，串口用于ASCII码字符的传输。通信使用3根线完成：（1）地线，（2）发送，（3）接收。由于串口通信是异步的，端口能够在一根线上发送数据同时在另一根线上接收数据。其
-
-
0下载：
This file recieves the serial data from the UART and forward to Serial To Parallel module
-
-
0下载：
This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
-
-
0下载：
串行转并行的VHDL源代码，结构化编程，学习模块化编程和实用性都很大。-Serial transfer parallel VHDL source code, structured programming, modular programming and practical learning are great.
-
-
0下载：
并/串转换的VHDL源代码，其中包括完整的QUARTUS2工程，还有正确的仿真波形。串行，并行数据
-Serial/parallel conversion ，VHDL source code, including complete QUARTUS2 project, and the correct simulation waveform file.
-
-
0下载：
its code for converting serial to parallel processing data
-
-
0下载：
The data in the shift register in shift pulses can move or by bit right next moves left, data can be parallel input, parallel output, also can serial input, serial output, still can parallel input, output, serial input, serial, parallel output is fle
-
-
0下载：
用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based
-
-
1下载：
ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明：
Filename Function
-----------------------------------------------------
dds_controller.vhd top entity, opcode decoding
ddslib.vhd configuration,opcode definition
dds_serial.vhd parallel to s
-
-
0下载：
This page of VHDL source code covers 2 bit parallel to serial vhdl code and provides link to 2 bit serial to parallel conversion.
-
-
0下载：
SERIAL TO PARALLEL VHDL CODE
-
