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simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
risc_cpu
- This an example of simple RISC CPU implemented in SystemC.-This is an example of simple RISC CPU implemented in SystemC.
risc_cpu
- SystemC实现的一个精简指令CPU模型-risc CPU model in systemc
RiscCpuA
- systemC模仿RISC CPU的简单功能-system C foumulate the simple function of RISC CPU
RiscCpuB
- systemC模仿RISC CPU的一般功能-systemC imitate RISC CPU' s general functions
RiscCpuC
- systemC模仿RISC CPU的完全功能，包括时序，信号-systemC imitate fully functional RISC CPU, including the timing, signal