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2下载：
Turbo Decoder Release 0.3
* Double binary, DVB-RCS code
* Soft Output Viterbi Algorithm
* MyHDL cycle/bit accurate model
* Synthesizable VHDL model
-Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * M
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turbo encode and decoder
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Energy efficient for turbo encoder decoder
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In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo
equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of
joint equalization and deco
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The turbo enocoder and turbo decoder is design in VHDL code.
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investigating the performances and complexities
of the various SISO algorithms. a turbo decoder with the selected SISO algorithm is designed and implemented using VHDL as design entry and simulation language
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基于sova算法的Turbo码解码VHDL工程文件，非常经典，包含Python高层仿真代码。-Turbo Decoder Release 0.3
MAIN FEATURES
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* Double binary, DVB-RCS code
* Soft Output Viterbi Algorithm
* MyHDL cycle/bit accurate model
* Synthesizabl
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