搜索资源列表
卷积码、CRC
- 卷积码的C源程序，包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
convcode_interleaving.rar
- 一个实现了213卷积码编码和卷积交织的verilog程序，编译通过,An implementation of 213 convlution code and interleaving on verilog HDL.
convolution_encoder_VHDL
- 卷积码编译码,由SERVICE、PSDU、TAIL和PAD域组成的DATA域应进行卷积编码，码率应根据所需的传输速率从R=1/2,2/3,3/4中选择-for 802.11a simulation WLAN FEC convolution_encoder g0=133 g1=171 Rate 0:1/2 1:2/3 2:3/4 for 802.11a simulation
chengxu
- 一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
juanjiqi
- 这是一个卷积器的设计，源码值得好好地学习-This is a convolution design, source code should be a good learning
fangzhen
- 卷积码和循环码的verilog编码以及仿真结果图，-Convolutional codes and cyclic codes and the coding verilog simulation results map
cc_encode
- 卷积码，并行编码，FPGA，通过了测试验证-CC Code， Parallel Coding， FPGA
Convolutionalencoder
- 应用VHDL语言实现的卷积编码器的应用程序-Application of VHDL language implementation of the convolutional encoder applications
conv.vhd
- 卷积编码的VHDL代码，公司内部资料，不是个人随便编写的-VHDL code of convolutional encoding
viterbi213
- 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
juanjiandviterbi
- 介绍了目前在数字无线通信中常用的一种向前纠错编码卷积码编码和Viterbi解码的原 理，并采用TOP—DOWN的设计思想，利用相关的EDA工具软件进行设计。并将卷积码编码器、 Viterbi译码器设计下载到Ahera公司的FPGA芯片上进行仿真，得到了预期的设计结果。-Viterbi
convencode2
- 卷积码（2，1，3）编码过程。代码清晰简单，对应人民邮电版《通信原理》中卷积码编码过程-Convolutional code (2,1,3) encoder. Code is clear and straightforward, Telecommunications for the corresponding version of " Communication Principle" in the process of convolutional coding
123
- 将通过仿真的VHDL 程序下载到FPGA 芯片EPF10K10LC84-3 上，取得了较为满意的结果。本设计选择的(3,1,2)卷积码和（2,1,1）卷积码,都是极具代表性的卷积码。因为卷积码具有相似的结构和特点，所以(3,1,2)卷积编码器和（2,1,1）卷积解码器的设计思想，具有普遍适用性。-Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained s
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
FPGA-convolutions-encoder
- 卷积码是数字通信中很重要的一种差错控制编码 具有很好的性能,用硬件的形式描述具有速度快，便于修改的优点，通过该种方法设，计的编码器经测试运行可靠正确。-Convolutional codes are very important in digital communication error control coding with a good performance, with the descr iption of the hardware in the form of a fast, eas
encoder
- 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,
基于VHDL卷积交织器的设计与实现
- 基于VHDL卷积交织器的设计与实现(1)(Design and implementation of convolution Interleaver Based on VHDL)