几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code

比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program

cpu控制器用vhdl代码编写组成原理的控制器组合逻辑-cpu controller using vhdl coding theory composed of combinational logic controller

vhdl 编写的cpu 代码, 详细说明了各个部分的功能及所有对应的代码，对cpu架构的学习和vhdl 编程有很大帮助(vhdl code for simple CPU)