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shixian.rar
- 该文件是一份本人设计的实验报告，报告内详细说明了用VHDL语言，设计一个三位动态显示的计数器。采用模块化得设计，设计通过了仿真以及下载实现。总的文件是：shixian.vhd,下面包括四个元件：jishu1000.vhd,xzqh.vhd,senvedec.vhd,disp.vhd.,this paper uses vhdl to complement a design about how to make three leds display at the same time.
IIRfilterFPGA
- 介绍了IIR 滤波器的FPGA 实现方法,给出了 IIR 数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法,并用VHDL和FPGA 器件实现了IIR 数字滤波。-Introduction of the IIR filter FPGA implementation method of IIR digital filter timing control, delay, multiplication and accumulation complement the four modules
16Point-FFT
- 16点FFT VHDL源程序，The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a
SR_Latch
- RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit i
convolution_calculator_4_bits
- convolution is important and is widely used in digital signal processing.For example, in LTI system. Input two sequences of 8-bit 2 s complement signed numbers with length 2~8. the input values range is -128~127.
booth
- 布斯公式求补码乘法的算法，用VHDL语言编写-booth algrithm, work out the 2 s complement mulitplier using VHDL
fenpinqi
- 用VHDL设计/具有分频作用，与其它模块相得益彰！-With the frequency effect, with other modules complement each other!
digital-quadrature-down-converter
- 基于FPGA的数字正交下变频器设计,在ALTERA的DE2开发板上设计一个多相滤波结构数字正交变换器。其中多相滤波模块是最关键模块，该模块将64阶滤波器的系数分成奇偶两路，并通过VHDL常数的方式存储在模块内部。这些常数是通过在MATLAB中调用FDATool，根据滤波器的参数要求来生成的。这些浮点格式的滤波器系数还需要在MATLAB中计算成二进制补码的形式，才可以存储在模块中。-FPGA-based digital quadrature down-converter design, ALTER
cc14585
- 用vhdl语言编译一个8位二进制求补器 对输入的数字进行求补运算-Vhdl language compiler with an 8-bit binary complement of the input device to complement the number of operations
complement
- 用vhdl语言编译一个8位二进制求补器实现求补运算-Vhdl language compiler with an 8-bit binary complement complement computing device to achieve
div_32bits
- 以ISE为平台，VHDL语言编写的32位补码整数除法器模块，只需在Top模块中调用即可-As a platform to ISE, VHDL language complement 32-bit integer division module, simply call the module to Top
Vhdl1
- calculating of iD & iQ, with ia & ib in 2 s complement
1bitAdder
- vhdl code for multiplication of two sign digit and every other 2 s complement numbers and every number in nega binary form
vhdl-eg
- It is a nor gate.That is extensively used in digital circuits. it is a complement of OR gate.
vhdl-complement
- vhdl交通灯控制电路实现，和LCNT8实现，程序为单进程，可读性好，技巧性高。-vhdl traffic light control circuit and LCNT8 achieve the program as a single process, readability skill.
VHDL_Bough_64-bit-twos-complement-multiplier
- VHDL Ccode_Booth two s complement multiplication
BUMA_TO_YUANMA
- VHDL程序，用于实现补码和原码的转换，分为测试程序和源程序。-The FPGA code is used to achieve transferring bewteen complement code and original code.
EDA
- 采用一种基于FPGA的IIR数字滤波器的设计方案,通过QuartusⅡ的设计平台，采用自顶向下的模块化设计思想将整个IIR数字滤波器分为：时序控制、延时、补码乘加和累加四个功能模块。分别对各模块采用VHDL进行描述后，进行了仿真和综合。-IIR digital filter using a FPGA-based design, analyzes the theory and design method of IIR digital filter, then through QuartusⅡ de
SOC_Code
- 加法器，原码补码乘法器，ROM设计，PC计数器等的VHDL详细代码-The source-code complement adder, multiplier, ROM design, such as PC counter of VHDL code in detail