搜索资源列表
sdram_vhdl_lattice.rar
- lattice sdram 控制器VHDL源代码,Sound code of Lattice Sdram Controller based on VHDL
MICO8_DEMO_03_18_08.ZIP
- Lattice 超精简8位软核CPU--Mico8，开放所有源代码，包括VHDL，编译器，支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。,Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to supp
DDR_SDRAM.rar
- DDR RAM控制器的VHDL源码, 实现平台是Lattice FPGA,DDR RAM controller VHDL source code, the realization of Lattice FPGA platform is
music
- 设计并调试好一个能产生”梁祝”曲子的音乐发生器，并用EDA实验开发系统（拟采用的实验芯片的型号可选Altera的MAX7000系列的 EPM7128 CPLD ，FLEX10K系列的EPF10K10LC84-3 FPGA， ACEX1K系列的 EP1K30 FPGA，Xinlinx 的XC9500系列的XC95108 CPLD，Lattice的ispLSI1000系列的1032E CPLD）进行硬件验证。 设计思路 根据系统提供的时钟源引入一个12MHZ时钟的基准频率，对其进行各种分频
DDR_SDRAM
- ddr sdram 的控制程序，lattice的，比较好用的，大家-ddr sdram control program, lattice, and relatively easy to use, and we look
UART_VHDL_Verilog_Lattice
- 本压缩包中含有串口程序的VHDL,Verilog，Lattice三种版本的代码，均已实现。在压缩包中，含有非常详细的串口的实现规格。各种版本的代码中，含有完成的源文件，测试文件，模拟文件。-This compressed package contains serial process VHDL, Verilog, Lattice three versions of the code, have been achieved. In the compressed package, contains
vhd_divider
- lattice isplever7竟然没有除法库,只好在网上找了老外写的vhdl除法器-lattice isplever7 Treasury did not divide, so the Internet to find a foreigner to write the VHDL divider
xp2demo
- lattice xp2 系列开发板带源码，有需要的可依进行设计参考！-lattice xp2 Series development board with source code, need-based reference design!
lattice
- 本程序是用VHDL编写，用于实现点阵显示功能。-This procedure is used VHDL to prepare for the realization of dot-matrix display.
ispLEVER
- vhdl 帮助文档 （中文） vhdl 帮助文档 （中文）-VHDL help documents (in Chinese) vhdl assist document (English)
ledhzxs
- 以FPGA芯片为核心，扩展必要的外围电路，制作一个16*16LED点阵的汉字显示屏，使之能显示16*16LED点阵的汉字4个，如“一”，“二”，“三”，“四”等。要求显示的汉字无闪烁。每个汉字停留时间1秒。-To FPGA chip as the core, the expansion of the necessary external circuit, producing a lattice of 16* 16LED display of Chinese characters so that
LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
Lattice-Machxo-FPGA-Loader
- Application note (source code + documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP programming of a parallel flash.-Application note (source code+ documentation) about how to use an FPGA (Lattice Machxo) to perform a ISP progra
VHDL-FPGA-xilinx-altera-frily
- VHDL的经典经验。相当的不错，一个多年开发FPGA的工程师自己的记录，适用于ALTERA,XILINX,LATTICE等FPGA的开发。希望对大家有用。-VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera VHDL-xilinx-fpga-altera
uart16450
- uart 16450合集,xilin altera lattice-collection of uart controller 16450
sd_hd_sdi_demo
- lattice的SDI DEMO板工程源代码，HD/SD自适应，内有彩条自产生源-designed for lattice sdi
dot
- 在和众达SEED-XDTK平台上，基于XC4Vsx25的点阵驱动程序。-In and Jones SEED-XDTK platform, based on the lattice XC4Vsx25 driver.
hanzi1
- 用VHDL编写的使晶体点阵显示汉字的程序-Written in VHDL, the crystal lattice display Chinese characters of the program
matrix
- 该源代码是控制16*16点阵的VHDL语言描述，可以让点阵连续显示设置的汉字。-The source code is to control 16* 16 lattice VHDL language descr iption, allowing a continuous dot-matrix display settings of the characters.
74HC595-lattice-clock
- 74HC595点阵时钟：使用74HC595芯片控制的16*16点阵时钟，流动显示时分秒，单片机：STC12C5A60S2-74HC595 lattice clock: using 74HC595 chip control 16* 16 dot matrix clock, mobile display minutes and seconds, the microcontroller: STC12C5A60S2