资源列表
50M
- verilog 语言写的分频模块，实现用50Mhz的时钟频率分出1hz的频率，也就是一秒的频率-verilog language sub-frequency module, using the 50Mhz clock frequency 1hz separation, that is, the frequency of second
stopwatch
- 基于fpga的停表设计vudl编写，使用vhdl编写的.v文件。-the stopwatch based on fpga written with vhdl
Finit_state_machine_in_C
- C实现一个状态机,我做毕业设计，实现自组织网络，三个节点-Finit state machine implemented in C code
chepin
- 利用51单片机进行测频，分为测频与测周两种方案。10Hz到10KHz范围-Carried out using 51 single-chip frequency measurement, frequency measurement and the measurement is divided into the two-week program. Range of 10Hz to 10KHz
32-rip-adder
- A ripple carry adder allows you to add two 32-bit numbers
26204298SRAM-PINGPANG
- 一个用verilog写的简单的乒乓球程序，用来在VGA上显示小球和挡板-Using Verilog to write a simple table procedures, used in the VGA display of small ball and baffle
ChangeAD
- STC15f2k60s2实现8位AD采集-STC15f2k60s2 achieve 8 AD acquisition
shift-register
- VerilogHDL语言实现的普通寄存器-VerilogHDL language common register
PM2.5
- arduino 程序，此程序应用于pm2.5检测。-arduino, this procedure is applied pm2.5 testing.
007
- sr-04超声波测距模块测距c程序 可测量范围0.2-4m-of hcsr-04
LCD16x2 Interfacing
- This source VHDL code is used for control LCD16x2 on FPGA
lcd
- This source is used to control LCD 16x2 on FPGA board