资源列表
adder_n_bits
- vhdl entity adder of two words of nbits.
atmega16phasecorrectedpwm
- atmega16相位修正pwm产生所需寄存器配置方法-atmega16 phase-corrected pwm produce the desired configuration register
daddf
- DAC0832 接口电路程序，今天上午本人已验证，-DAC0832 interface circuit procedure, this morning I have verified,
biaojueqi
- 七段显示译码器，在学习中是一个经典案例，值得认真学习-Seven segment display decoder, in a classic case study worthy of serious study
clock
- 大学生篮球比赛30S计时器-30S college basketball game timer
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
ILOVEU
- 使用51单片机在一块8*8点阵led上动态显示“I LOVE U”和 ／＼／＼ ＼ ／ ＼／图案。-This is the code of displaying three English words-"I LOVE U"on a 8*8 dot matrix led by using a mcs51 microcontroler.
1
- 实现51单片机与51单片机以及PC机的通信过程。-Communication process to achieve 51 and 51 microcontroller and PC machines.
inter
- vxworks下PCI中断处理程序,该代码已经在6.8环境下调试通过-Under the environment of VxWorks PCI interrupt handling procedures
demodulation
- QPSK解调程序，verilog语言，基于FPGA的硬件描述语言-QPSK demodulation
code
- 动态扫描键盘，然后把按键结果显示在LCD上，相关使用去抖功能-Dynamic scan keyboard, and then the key results are displayed on the LCD, the use of the shake function
stc-uninterruptible-power-download
- stc单片机不断电下载程序方法,此方法无需修改电路，只需要加入几行代码就可以实现。-stc microcontroller UPS download method, this method does not need to modify the circuit, only you need to add a few lines of code can be achieved.