资源列表
32位-33M 从模式(target)PCI接口参考设计_lattice
- 32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32 / route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
8051参考设计_Oregano System 提供_vhdl
- 8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
CRC校验参考设计_xilinx_verilog
- IEEE 802.3 Cyclic Redundancy Check参考设计，xilinx提供-IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
CRC校验参考设计_xilinx_vhdl
- 可配置CRC参考设计 xilinx提供的VHDL-configurable CRC reference design for Xilinx VHDL
DS12887时钟芯片编程
- 利用程序中的函数，来读取时钟芯片的秒、分、时、日、月、年、世纪，亦能对其设置时间日期。-procedures for the use of function, to read clock chip seconds, hours, days, months, years, centuries, but also the date of its set-up time.
红绿灯
- 模拟交通灯，并带有数字显示的程序。初始时全为红灯，显示“HELLO”字样。然后交通灯以“红绿、红黄、绿红、黄红”四种状态做循环，而且黄灯会闪烁，每种状态都带有到数记时。当按下P3_2时，变成“红红”状态，并显示“STOP”字样！ -simulated traffic lights and figures with the procedure. When all of the initial red, shows that the "hello" words. Then t
ddr_verilog_xilinx
- DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
洗衣机
- 通过不同的二极管亮，表示洗衣机的不同状态。如正转、反转、洗条、干衣。按下P3_3时，会停止。 -through different diode light, washing machines, said the different states. Who is changed, and turned around, washing, drying. Press P3_3, would cease.
显示0到F
- 利用串行驱动数码显示每位从0显示到F，到灭循环显示，要求1秒更新一次。-drive using serial digital display shows each from 0 to F, to eliminate cycle, a request updated seconds.
dds_quicklogic
- 直接频率合成，Quicklogic提供,部分源文件是Quicklogic 专用文件-direct frequency synthesis, pioneered provide some source document is dedicated ESP
I2C总线控制器 altera提供-VHDL
- I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code
PCI总线仲裁参考设计，Quicklogic提供
- PCI总线仲裁参考设计，Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code