资源列表
iir
- IIR50HZ的数字陷波器的FPGA实现-IIR50HZ digital notch filter implementation in FPGA
counter-CPLD
- CPLD学习，用VHDL,应用EPM7032,一个138，373和273的例程-CPLD study, using VHDL, application EPM7032, one of the routines 138,373, and 273
8bit_RISC_CPU_RTL_Code
- 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
hdb3
- 这是一个很全的HDB3译码的verilog程序，用于FPGA入门所用，verilog的入门很好的程序-This is a very wide of the HDB3 decoding verilog program for entry-FPGA used, verilog entry procedures for good
clock
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
pulses_in
- VHDL实现两个脉冲间隔时间的检测，输出单位毫秒，测试成功。-VHDL realization of two-pulse interval of the test, the output units of milliseconds, the test successfully.
nios_led
- 基于FPGA的SOPC嵌入式的流水灯的实现。-Embedded FPGA-based SOPC flow light implementation.
bit_synchronize
- 位同步例程源代码,FPGA应用领域，Verilog-Bit synchronization routines source code, FPGA applications, Verilog
jtag
- Fpga开发应用，jtag方面的源代码，VHDL-Fpga development and application, jtag in the source code, VHDL
IPcore
- 非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
cpu_16bit
- design cpu 16 bits by verilog HDL.
szdyb
- 基于Verilog HDL的数字电压表的程序-Verilog HDL-based procedures for the digital voltmeter