资源列表
PipelineSim
- 这是用VerilogHDL写的一个MIPS处理器。-It is written with a MIPS processor VerilogHDL.
jpeg_verilog
- Jpeg压缩的Verilog代码，小图片-Jpeg compression of the Verilog code
bpsk_fpga
- 在FPGA上实现BPSK信号的解调，全部用VHDL语言编写，非常实用。-Implemented on the FPGA BPSK signal demodulation, all with the VHDL language, very useful.
SPI
- 基于verilog语言的 SPI接口实现. 有很好的说明.-Verilog language based SPI interface. Have a good descr iption.
danzhouqiCPU
- VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
F10-Single-Cycle-MIPS
- This a verilog code of single cycle mips-This is a verilog code of single cycle mips
AES_test
- verilog AES解密 ACTEL FPGA-verilog AES ACTEL FPGA
illinoi_arm7
- 一种ARM IP core，国外一个论坛上载下来的，希望能有所用处-A ARM IP core, a forum set off abroad, and hope to be useful
fftip
- 2008-2009年优秀硕士论文之：基于FPGA的高性能32位浮点FFT IP核的开发-Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development
fir6dlms
- lms算法，自适应滤波器中使用fir滤波器对信号的码间干扰进行均衡-lms
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.