资源列表
jiaotongdeng
- 简易的交通灯程序，适用于刚接触VHDL的人学习，易懂好学。-Simple traffic light program, for people new to VHDL to learn, easy to understand studious.
prbs
- verilog 格式的prbs数据。可以用于对发射机和接收机的误码率的测试-verilog format prbs data. Can be used for the testing of the transmitter and receiver BER
myfir
- verilog编写的16阶升余弦滤波器 采用直接型结构实现 对方波进行滤波 输出波形 含testbench文件-order raised cosine filter verilog written 16 direct-type structure to achieve the other wave filtering the output waveform containing testbench file
System-Verilog-and-HDL-skills
- 这个教程讲了如何用SystemVerilog写一个CPU，这个教程是和视频专辑http://i.youku.com/u/UMTExNzExOTgw/videos一起使用的，而且里面讲了一些FPGA的逻辑设计技巧-This tutorial about how to use SystemVerilog write a CPU, this tutorial is used in conjunction with, and the video album http://i.youku.com/u/UM
ft2232h_rollback
- FT2232H芯片usb循环读写 verilog 实现, 使用时pll可注释掉-FT2232H the chips usb cycle read and write verilog achieve
eetop[1].cn_axibusregslice
- axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
uvm-1.1d.tar
- UVM World 官方发布的UVM（通用验证方法学）的源代码，基于SystemVerilog，用于ASIC Verification。2013-03最新发布版本uvm-1.1d.tar.gz-The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03
digital_lock
- 数字密码锁verilog源代码，包括键盘输入，控制模块，和显示模块。-Digital code lock verilog
xapp1015
- SDI接口的VHDL实现，XILINX官网的设计参考-SDI interface VHDL realize XILINX official website design reference
conv_12_adpcm
- adpcm编码verilog程序,包含pcm转换模块、adpcm编码输出模块-ADPCM coding verilog procedures, including PCM conversion module, ADPCM encoding output module
VeriRISC_CPU_Verilog
- Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo
channel_loss
- 数字中频接收机,有助于您加深对多速率信号处理机中频数字接收机设计的理解-IF digital receiver can help U understand the principle of digital receiver.