资源列表
hdl-master
- ADI ad9361 vivado 下源代码-ADI ad9361 vivado source code
AD_ID
- ad7175的测试spi通讯是否正常的verilog HDL程序，读取ad7175中的id寄存器值。-ad7175 spi communication test whether the normal verilog HDL program that reads the ad7175 id register values.
10_CMOS_OV7725_RGB640480
- CMOS_OV7725_RGB640480 驱动源码 verilog语言，编译通过，有需要的拿去用-CMOS_OV7725_RGB640480 source code
Uart design with application file
- user defined Baudrate with changing in run time
fir filter vhdl code
- FIR filter design using Matlab Coefficient file and RTL design for FIR filter Design
AD7606
- AD7606的状态机驱动，并口模式，verilog代码，可正常使用。-AD7606 state machine drive, verilog code, can be normal use.
latticeECP3-serdes-test-code
- lattice ECP3系列高速FPGA serdes测试代码-lattice ECP3 series high speed serdes test code
OWIRE
- OWIRE verilog代码，实现了单总线上的通信传输的HDL顶层，子模块设计和testbench内容-The code of 1wire bus
ds18b20
- 完成DS18B20单总线温度传感芯片的控制和读取，将数据16位并行传出-Complete chip DS18B20 single bus temperature sensor control and read, 16 bit parallel data coming
fft_ifft
- fft and ifft code in verilog
eth
- 基于verilog语言的以太网接口的fpga实现，用在无线通信领域，供参考-The Ethernet interface based on verilog language fpga implementation, used in the field of wireless communications, for your reference
自定义PWM IP核，符合avalon总线
- 适合初学qsys、nios者，含tb文件，仿真通过，无bug