资源列表
encode_64_66
- 自编的64B/66B编码程序，下次上传解码程序。-the 64B/66B coding process is written by myself, i will upload the decoding process next time.
eetop.cn_m8051ew.tar
- M8051EW文档及源代码程序，很难搞到的！-M8051EW documentation and source code, hard to come by it!
verilogCRC32
- 32位bit输入的CRC32校验，verilog的代码，以及modelsim的testbench代码-The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench
Motion_control
- 用verilog语言编写的步进电机加减速控制算法，可选择梯形曲线或S型曲线算法-Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm
dda
- 该程序描述了运用FPGA 实现DDA圆弧插补运算-FPGA DDA
Sender
- 直序扩频通信发送部分的源代码，用verilog编的，包括信源模块、扩频模块、极性变换模块和DDS调制模块-Direct sequence spread spectrum communication sent part of the source code, compiled with verilog source modules, spread spectrum modules, polarity transform module and DDS modulation module
BCD-counter
- 一个2位的BCD码十进制加法计数器电路，输入为时钟信号CLK，进位 输入信号CIN，每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT，输入时钟信号CLK用固定时钟，进位输入信号CIN. -A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output s
ulpiereport.tar
- 开源的ULPI IP核，可用于USB3300芯片的开发-openSource ULPI IP core which could be used for USB3300 chip development
LMS
- 用verilog编写的lms算法。可实现自适应滤波功能-Lms algorithm written in verilog. Adaptive filtering can be achieved
verilog-master-files
- Verilog master files of AMBA axi interface
STFT
- 短时傅里叶变换的FPGA实现零重复度使用了fft的IP核设计-When the Fourier transform of the FPGA to achieve zero repeatability using fft IP core design
jtag
- verilog语言编写的jtag（边界扫描模块），初学的时候可以-verilog language jtag (boundary scan module), a novice when you can look