资源列表
memristor
- 忆阻器的SPICE建模模型说明及仿真结果说明-Memristor SPICE modeling and simulation results show that the model describes
CAN_IP.rar
- 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。,This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
FPGA.rar
- 关于FPGA查找表内部结构的介绍，对查找表的建立与使用也有初步讲解 ,FPGA lookup table on the internal structure, the look-up table for the establishment and initial on the use of
DW8051.rar
- Synopsys 公司的DW8051源代码，用verilog编写的，代码很完整，可以仿真，对采用8051核做嵌入式的人很有帮助,Synopsys company DW8051 source code, written with Verilog, the code is complete, can be simulated using 8051 nuclear helpful people who do Embedded
FPGAAD9280LED.rar
- 用FPGA cyclone控制AD9280后，将结果用LED的明暗来表示，8位数据分两次显示。,AD9280 control using FPGAcyclone will be the result of the use of LED lighting to show that, in two 8-bit data display.
baseband_verilog.rar
- verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
cordic.rar
- 使用CORDIC算法求算反正切值，非常实用，大家可以下来,The use of CORDIC algorithm calculating arctangent value, very useful, we can down
elevltor
- 八层电梯的控制器，verilog实现。内附有详细源码。--The controller of three 8-level elevators, designed with Verilog. The design is detailedly represented in the DOC as well as the source code.
fpga_jpeg
- 图像jpeg压缩算法,用verilog HDL在FPGA上的实现 -Jpeg image compression algorithm, using verilog HDL Implementation in FPGA
MIPS
- 组成原理大作业--基于MIPS的运算器设计，内附详细设计文档，包含设计文档和使用手册，主程序，测试程序，还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条，用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and u
16QAM
- 16QAM调制与解调的Verilog语言的功能实现-the realization of 16QAM modulation and demodulation on Verilog language
FPGA
- 结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机-Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s i