资源列表
dds1
- 数字合成函数发生器 初学者最好的教程DDS-dds
PSKdemodulation
- 利用硬件描述语言VHDL实现PSK信号的调制-A VHDL program to realize the PSK demodulation of digital signals
task_calls
- task_calls for verilog
cal
- 设计一个十进制计数器，由0到9进行循环计数，同时将计数结果通过数码管显示出来-Design of a decimal counter, from 0 to 9 for cycle counting, while counting resulted in the adoption of digital tube display
CH_Function
- Para calcular la funcion CH del algoritmo SHA
stm
- 用verilog语言设计一个二进制序列检测电路， 当输入有连续“1011”出现时有输出为‘1’， 否则为‘0’.-Verilog language used to design a binary sequence detection circuit, a continuous input " 1011" appears when the output is ' 1 ' , otherwise ' 0' .
counter60
- 六十进制计数器的VHDL源程序代码，很实用-Six decimal counter VHDL source code, very useful
alu
- An ALU with two inputs a and b and four basic ALU functions: output=a+1 or a+b+1 or b or a+b. Using a 2 bit input "sel" to select one function.
pri_encoder_using_if
- encoder using if - verilog
SAMD20_Aceelerometer
- SAMD20 Program for Accelerometer valves detection.
xilinx_license_2015
- Vivado Design Suite v2015.4版本license-the license of Vivado Design Suite v2015.4
array_mult
- VHDL code for array multiplier