资源列表
1302
- 1302时钟芯片驱动程序，显示年月日星期，包括液晶显示程序和数字转换程序-1302 clock chip driver, day of show week, including liquid crystal display processes and procedures for digital conversion
Moxa_TCP.RAR
- MOXA embedded linux TCP example
key
- 4*3矩阵键盘扫描，按下一个键在数码管上显示相应键值-4* 3 matrix keyboard scanning, press a key on the digital tube displays the corresponding key
595test
- 用89c52通过两片74hc595控制4位led显示-89c52 using two 74hc595 control through 4 led display
comm1
- MSP430的SPI的通信实现程序，非常繁复 ！-MSP430' s SPI communications implementation process is very complicated!
MSDev98
- MSDev98如题目所示，MSDev98-MSDev98 as the title shows, MSDev98
IPcore_fifo_testbench
- 我自己写的一个verilog的fifo测试程序，配合xilinx的fifo ip核-I own the fifo write a verilog test procedures, with the fifo ip nuclear xilinx
vikash_lift---Copy
- THIS THE SOURCE CODE OF LIFT CONTROLLER IN VHDL-THIS IS THE SOURCE CODE OF LIFT CONTROLLER IN VHDL
sram_test
- sram读写操作，时序规范说明和详解，代码说明很详细，很适合新手-sram read and write operations, the timing specification and Xiangjie code describing in great detail, it is suitable for novice
tim-input-catpure-counter
- 定时器输入捕获tim input catpure counter-tim input catpure counter
mat_det
- 基于FPGA的3阶矩阵求行列式的verilog代码-FPGA-based third-order matrix determinant verilog code
dpll
- 数字锁相环 dpll的 编译通过,使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法-Digital phase-locked loop dpll compiler through the use of verilog HDL language on the phase-locked loop FPGA-based digital system design, as well as its performance analysis