资源列表
KESHEPLC
- 通过PLC来与过程控制设备通信 控制过程控制设备的工作-KNAKNAN
12C887
- 12887shizhongde 驱动大家好好学习 网名共同进步 123456789 一定可以成功的
ALU
- ALU logic using Verilog
ADD
- ADD instruction for the HC08 Target
code_lock
- 密码锁,内部有密码的初始输入与设置密码,还有密码的鉴定.-Lock, internal code of the initial input and set the password, as well as the identification code.
uart
- 用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。-a veriog program completed on FPGA to contrlo a uart to communicaton with a computer
dac
- Delta sigma DAC for use in FPGA includes Testbench
bpsk
- implementation of bpsk using dsk6713
clock
- 采用FPGA实现数字钟功能，包括调时调分整点报时等功能。-FPGA Implementation of a digital clock function, including the tune when the tune points the whole point timekeeping functions.
dac_test
- DAC_TLC5620测试模块，verilog语言-module of texting DAC_TLC5620
vga
- FPGA board universal VGA block
equalizer
- This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.