资源列表
ssd1298
- ssd1298初始化代码，TFT液晶驱动，用于手机和MP4的开发。
KEY
- 2乘8按键扫描程序 4个IO口 74LS164串行数据端 时钟端 两个普通IO口
Exp3_2
- 单片机汇编语言实验,主要是有关于怎样采用汇编语言来实现对数值的处理-asm experiment
state_classic
- 用VHDL语言编写的语言,可以利用MODELSIM进行仿真.对于初学者,则更有参考价值.-prepared using the VHDL language, we can use MODELSIM simulation. For beginners, the more valuable reference.
tmroinitial
- 本程序是关于PIC定时中断服务程序，希望对大家有帮助。-TIME0
bcd
- EDA 十进制计数器、BCD VHDL源代码-EDA decimal counter VHDL source code
FIR
- The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. Th
myinterpolation
- 复杂的插值函数，用于颜色空间转换 verilog-The complex interpolation function for color space conversion verilog
crc16_8
- crc16,数据位宽为8，verilog编码-crc16 ,datawidth is 8,coding by verilog
chuzucheVHDL
- 用VHDL写的出租车计价程序，拥有详细的说明-Taximeter written with VHDL program, has a detailed descr iption of
QDEC
- 旋转编码器的正交解码程序，使用VHDL语言--- This decoder in VHDL samples the signals using all four available edges of -- A and B. E.g. sample(B) on rising(A), sample(A) on falling(B), sample(B) on -- falling(A), and sample(A) on rising(B).
fir
- FIR滤波器的FPGA实现，串行移位算法，运行周期长但资源利用率低。-FIR filter FPGA, serial shift algorithm, but the long-running cycle of low resource utilization.