资源列表
CAT24C128
- 这是snap语言，演示通过I2C与串行EEPROM芯片接口-This is a snap language, presentation and through the I2C serial EEPROM chip interface
ram_old
- 用来测试cpu的ram代码 其中包括几十条指令 cpu的vhdl也在本站有下-Cpu the ram used to test the code, including dozens of VHDL cpu instructions also have a website under the
brentkung_32
- 32 bit brentkung adder tr-32 bit brentkung adder tree
5_lined_cpu
- 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
spi
- 串行外围接口，可用于FPGA器件与串行A/D/A的通信-Serial peripheral interface, which can be used for communication between FPGA devices and serial A/D/A
MULTIPLIER
- 基于VHDL硬件描述语言设计的乘法器，位数可以修改-VHDL hardware descr iption language based on the design of the multiplier, the median can be modified
dds
- DDS数字函数信号发生器，采用VHDL编写，可以产生正弦波、锯齿波、三角波信号，信号的频率和相位都可调。-DDS Digital Function Generator using VHDL write, you can produce sine, sawtooth, triangle wave signal, the signal s frequency and phase are adjustable.
16
- 编写两个十六位数的加法程序。 有两个十六位无符号数，分别存放在从20H和30H开始的数据区中，低八位先存，高八位在后，和存于R3（高八位）和R4（低八位），进位位存于R2。-Write two sixteen digits addition program. There are two 16 bit unsigned number, respectively in from 20 h and 30 h began to data area, low eight put first, hi
motor2
- PLC程序。是关于电机正转、停止，然后再反转的plc控制编码。简单实用。-PLC program. Motor forward, stop, and then re-reversed plc control coding. Simple and practical.
miaobiao
- 用外部中断1和0做按键，来控制秒表停止和清零-External interrupt 1 and 0 keys do to control the stopwatch stopped and cleared
LP_DMA_DSP
- adi ts201的实验 可以参考 入门ts201 dma传数据-adi ts201 experiments can refer to pass data entry ts201 dma