资源列表
part11
- s3c44b0 qudong 程序原码 以及各种驱动接口的原码 书中自带的程序-s3c44b0 qudong procedures original code-driven interface, as well as the original book, bringing their code procedures
div_clk
- 主时钟为15.36MHz的带选通的8位输出分频器，可得到100Hz,120Hz,1kHz,10kHz的频率-Master clock for the 15.36MHz band strobe output 8-bit prescaler, can be 100Hz, 120Hz, 1kHz, 10kHz frequency
STRINGS
- Bascom 8051 example program-Bascom 8051 example program
initializationprogramofADS8364(1)
- 配置GPIOE为XINT1，XINT2，由于不知道要上载5次，所以一次把五个程序都上载了，现在重新依次上载-GPIOE configuration for XINT1, XINT2, as a result do not know want to upload 5 times, so the first five procedures to upload, and now in order to re-upload
w4_4
- adaptive encoding and decoding depending on the channel SNR
transfer
- 实现UART的发送功能，采用了状态机来描述其功能。-Achieve UART transmit function, using the state machine to describe its function.
cordic-verilog
- 用Verilog写的cordic相位鉴别，采用8级的流水线的硬件设计-Written using Verilog cordic phase identification, using 8-level hardware design of the pipeline
jtd
- c51控制的交通灯程序，由8279驱动数码管显示。-c51-controlled traffic lights program, driven by the 8279 digital display.
keyboard
- verilog FPGA开发板4*4键盘代码，正确可实现-4*4keyboard diven by verilog
shejilegeshangxiazidongkongzhi
- Verilog 的设计的程序。反复看了很久，电梯设计很是实用性强的一个程序，现在分享给大家，很多实验室做设计的时候需要，希望可以用到-The Verilog design program. Repeatedly looked for a long time, elevator design is very practical program for everyone now share many laboratory design needs can be used
hello_uart
- Uart接口测试程序，Xilinx参考设计，ML507硬件测试通过.--Uart interface test code，Xilinx reference design，tested on ML507 platform.
zhs_SCI
- DSP tms320f28335 对SCI程序的设置-DSP28335 settings SCI program