资源列表
EPP
- 并口的EPP协议，与外部的FIFO的empty,full信号共同控制数据传输-of EPP parallel port agreement with the external FIFO empty, full common control signal data transmission
pinlvji
- 频率计，vhdl语言， ispDesignEXPERT
ads2
- ADS8325caiyang konfgzhi
TIM0
- str912定时器0的输出比较功能--实现78.125us中断一次IRQ中断-str912 Timer 0 output compare function- to achieve a 78.125us interrupt IRQ interrupt
girassol
- Projeto de um Girassol.
i8255
- 8255的VHDL仿真实现的是串并接口的功能-8255' s VHDL Simulation is the string and the function of the interface
9850
- AD9850 程序实现信号产生，方波，三角波，正弦波的可调变换-AD9850 program
SVM
- 电机控制的SVPWM程序，经测试可以使用的，大家支持啊。-Motor of SVPWM control procedures, the test can be used, and we support the ah.
mod3
- verilog源代码，实现两种方法的模3运算。-verilog source code，to implement the calculation of mod-3 by two means.
pncode
- verilog hdl编写的伪随机序列产生程序；包含测试文件；-Verilog HDL；PN code
Timer0
- 利用CPU时间定时器0产生中断，在中断函数中实现AD的转换。-Use of CPU time timer 0 interrupt is generated, the interrupt function is implemented AD conversion.
uart_tx
- 硬件描述语言设计的串口发送源代码UART TX SOURCE CODE-Verilog HDL UART TX RTL SOURCE CODE