资源列表
statem
- 元件例化与层次设计，verilog 实例说明-components cases with the level of design, Verilog example
fet140_2
- MSP-FET430P140 Demo - Software Toggle P1.0-MSP-FET430P140 Demo-Toggle P1.0 Software
128×16ram
- VHDL程序设计的RAM存储器，双端口，128×16比特
add_ff8
- 利用触发器实现的，8位半加器的VHDL语言实现，适用于altera系列FPGA
PS2
- 设计一个计数器，信号频率为10MHZ，没10M个信号记一次数。-counter
1addto10
- 本程序是一个从1累加到10的小算法，用VHDL编写与实现-no
spi25
- 铁电SPI 读写 FPG 外挂SPI铁电存储器的读写控制代码.-FM25** SPI R/W
AD9957_Signal_Generate
- AD9957芯片通过FPGA配置的verilog程序,要自建工程，代码测试完全可用-AD9957 chip FPGA configuration verilog program, to be self-built project, code test is completely available
rxtx
- 串行通信程序，程序稳定可靠，分为好多模块代码写的不错，值得参考，-Serial communication program, the program is reliable, divided into a lot of module code written well worth considering.
phase_add
- 分频器，实现任意频率的分频，只需修改频率控制字,已经经过多次验证-Divider to achieve any frequency divider, simply modify the frequency control word, has been repeatedly verified
C702
- 控制HMC702的VHDL程序代码,实际使用是可以的，HMC MODE-HMC702 SPI VHDL code
Dijkstra
- 用verilog 实现求最短路的Dijkstra算法，用modelsim仿真通过，数据真确，-Dijkstra implemention with verilog base on FPGA