资源列表
collect
- 用verilog编写的max197这个AD转换的程序，在ISE综合仿真均通过。-max197, verilog
FA_4
- Full adder 4 vhdl code
wtf
- NS2 WIRELESS TRACE FILE
seg7_drv
- seg7 LED display driver
pblazeIDE_coe_example
- expample of picoBlazeIDE assembly of producing coe file for fpga
mux16_1
- VHDL code foe 16:1 MUX using structural modelling
decode
- 38译码器74ls13838译码器74ls138-Decoder 38 decoder 74ls13838 74ls138
chuan_to_bin
- 串转并，信号串转成并的VHDL实现，很有用。-String transfer and signal string and convert VHDL to achieve useful.
freq
- 等精度频率计的verilog实现，经过quartus编译-Verilog to achieve equal precision frequency meter
led-module
- 通过按键处理模块送来的信号，对led进行控制-Through the key processing module sent signals to control led
VHDL_32bit_full_adder
- VHDL code _32bit_full_adder
T1
- 用定时器T1的查询方式控制51单片机发出1KHz音频-Timer T1 controls the microcontroller 51 queries issued 1KHz Audio