资源列表
XF_TEST
- DSP 系统入门与实践一书中的实验之一,本实验的主要目的是让读者对DSP程序在DSP硬件上运行有一个直观的理解，同时也通过这个简单的程序来说明汇编语言的格式及其写法。 -DSP system portal and practice of a book, The main purpose of the experiment is to allow the reader to DSP procedures in DSP hardware to run a visual understanding
jxinyu
- 用单片机进行速度与里程的计数,就像出租车的计价器一样可以显示总里程,实时行驶速度等.-microprocessor with the speed and mileage of the count, like the taxi meter will show the same overall length, Real-time speed, and so on.
potel
- 这是个我的毕业实际 毕业实际 毕业实际 毕业实际-This is my graduation actual graduation actual graduation actual graduation actual graduation actual graduation actual graduation is the actual graduation International graduate actual graduation actual graduation actual grad
microwindows.example10
- 基于嵌入式图形库microwindows的简单示例程序10例-embedded graphics library based on the simple example microwindows procedures in 10 cases
microwindows.desktop
- 基于嵌入式图形库microwindows编写的一个简单的桌面程序-based on embedded graphics library microwindows prepared by a simple desktop procedure
AsmforARM
- ：some examples of assembler level programming for the ARM（produces an ELF executable file which can be loaded into an ARM debugger）-: some examples of assembler level programming f or the ARM (ELF produces an executable file whic h can be loaded into
databortfor2410
- 基于ARM920T内核的S3C2410下的databort（数据异常模式）程序，ARM所作-Based on ARM920T core of the S3C2410 databort (data anomaly pattern ) process by ARM
swifor2410
- 基于ARM920T内核的S3C2410下的SWI（软件中断）程序，ARM所作-Based on ARM920T core of the S3C2410 SWI (software interrupt) procedures, ARM made
SimpleforS3C2410
- 注意编译环境：ARM-Linux，这是一个为S3C2410入门者所写的简单但是较全面的源代码，编译时请注意相应参数的修改，学习S3C2410开发，从这里开始！-attention to the build environment : ARM-Linux. This is a S3C2410 for beginners written a simple but comprehensive source code, Please note that compile-time parameter ch
guessnumbergame
- 下载即可运行，适用于初学者学习。 这里是源码。下载到单片机可运行。需要加键盘和显示屏-operation can be downloaded applicable to beginners learning. Here is the source code. SCM can be downloaded to run. Need to increase the keyboard and display
myDoc1
- 本设 计 将 转换结束状态线STS与单片机的P1.7 相连，启动转换信号CE由单 片机的丽和丽相与所得，采用查询方式来读取AD574A的转换结果，由AO来 控制读取高8位和低4位。-the design will change end of the state line STS and SCM P1.7 connected, CE start converting signals from the MCU Laguna and Laguna phase proceeds, using i
vhdlcodes11
- FPGA/CPLD集成开发环境ise的使用详解 示例代码-FPGA / CPLD integrated development environment IDE ise the example code