资源列表
pipeline
- 自己写的c语言版的软件实现cpu的pipeline功能的程序。对于学习体系结构的同仁有好处。-himself wrote the c language version of the software cpu the pipeline functional procedures. Learning Architecture for the benefit of us.
huibidianzishizhong
- 汇编语言实现实用单片机电子钟的制作，包括时间的显示以及中断控制。-assembly language to achieve practical SCM electronic clock production, including the time of the show and interrupt control.
Hkbus16
- 多数位分频器.............................................可直接编译-Contents Paragraphs Page majority-Frequency Divider can be directly translated .......................
RG2051
- 用于接收红外摇控器和异步串行的8051单片机程序-for receiving infrared remote control and asynchronous serial 8051 of the procedures
cystart
- CY7C637xx CY7C637xxC Y7C637xxCY7C637-CY7C637xx CY7C637xxCY7C637xxCY7C637xx CY7C637
dllSmartCar
- 本程序是智能小车开发环境中的dll文件可以在Visual 平台下开发-this procedure is smart car development environment of dll file can be developed under Visual Platform
CU.v
- 用vlog语言编写的cpu控制器源代码，用于fpga的硬件编程实验-vlog language used in the preparation of cpu controller source code for programming fpga hardware experiments
mult8x8
- 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
mod6_cnt
- 一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
de_mux
- 一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer
mod6_divide
- 用VerilogHDL编写的，一个占空比为50％的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
cordic
- 用于实现sin，cos三角函数计数的VHDL程序代码-towards sin, cos trigonometry count VHDL code