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文件名称:8bitcpu_microprogrammed_vhdl

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    625.04kb
  • 已下载：
    0次
  • 提 供 者：
    邓****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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八位微程序结构的cpu设计 。 此为课堂设计，欢迎大家参考。 本人联系方式：justin_dengcn@126.com-8 cpu micro-structure of the design process. This is a lesson. please　Contact: justin_dengcn@126.com
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Finial(20100415)/ACC.bsf
Finial(20100415)/ACC.vhd
Finial(20100415)/ACCTest.bdf
Finial(20100415)/ACCtest.vwf
Finial(20100415)/BR.bsf
Finial(20100415)/BR.vhd
Finial(20100415)/cmp_state.ini
Finial(20100415)/ControlMem32Ini.mif
Finial(20100415)/ControlMemBDF.bdf
Finial(20100415)/ControlMemory.bsf
Finial(20100415)/ControlMemory.v
Finial(20100415)/ControlMemoryIni.mif
Finial(20100415)/ControlMemory_bb.v
Finial(20100415)/controlMemWave.vwf
Finial(20100415)/ControlUnit.bsf
Finial(20100415)/ControlUnit.vhd
Finial(20100415)/ControlUnitBlock.bdf
Finial(20100415)/CPU-Top.bdf
Finial(20100415)/CPU.qpf
Finial(20100415)/CPU.qws
Finial(20100415)/CPUDesign.asm.rpt
Finial(20100415)/CPUDesign.done
Finial(20100415)/CPUDesign.fit.eqn
Finial(20100415)/CPUDesign.fit.rpt
Finial(20100415)/CPUDesign.fit.summary
Finial(20100415)/CPUDesign.flow.rpt
Finial(20100415)/CPUDesign.map.eqn
Finial(20100415)/CPUDesign.map.rpt
Finial(20100415)/CPUDesign.map.summary
Finial(20100415)/CPUDesign.pin
Finial(20100415)/CPUDesign.pof
Finial(20100415)/CPUDesign.qsf
Finial(20100415)/CPUDesign.sim.rpt
Finial(20100415)/CPUDesign.sof
Finial(20100415)/CPUDesign.tan.rpt
Finial(20100415)/CPUDesign.tan.summary
Finial(20100415)/CPUTOPWAVE.vwf
Finial(20100415)/db/add_sub_0qh.tdf
Finial(20100415)/db/add_sub_1qh.tdf
Finial(20100415)/db/add_sub_5sh.tdf
Finial(20100415)/db/add_sub_lth.tdf
Finial(20100415)/db/altsyncram_d3r.tdf
Finial(20100415)/db/altsyncram_n8j.tdf
Finial(20100415)/db/altsyncram_nc31.tdf
Finial(20100415)/db/altsyncram_o8j.tdf
Finial(20100415)/db/altsyncram_p8j.tdf
Finial(20100415)/db/altsyncram_q8j.tdf
Finial(20100415)/db/altsyncram_r8j.tdf
Finial(20100415)/db/altsyncram_rrq.tdf
Finial(20100415)/db/altsyncram_s511.tdf
Finial(20100415)/db/CPU-Top0.rtl.mif
Finial(20100415)/db/CPU-Top1.rtl.mif
Finial(20100415)/db/CPUDesign.(0).cnf.cdb
Finial(20100415)/db/CPUDesign.(0).cnf.hdb
Finial(20100415)/db/CPUDesign.(1).cnf.cdb
Finial(20100415)/db/CPUDesign.(1).cnf.hdb
Finial(20100415)/db/CPUDesign.(10).cnf.cdb
Finial(20100415)/db/CPUDesign.(10).cnf.hdb
Finial(20100415)/db/CPUDesign.(11).cnf.cdb
Finial(20100415)/db/CPUDesign.(11).cnf.hdb
Finial(20100415)/db/CPUDesign.(12).cnf.cdb
Finial(20100415)/db/CPUDesign.(12).cnf.hdb
Finial(20100415)/db/CPUDesign.(13).cnf.cdb
Finial(20100415)/db/CPUDesign.(13).cnf.hdb
Finial(20100415)/db/CPUDesign.(14).cnf.cdb
Finial(20100415)/db/CPUDesign.(14).cnf.hdb
Finial(20100415)/db/CPUDesign.(15).cnf.cdb
Finial(20100415)/db/CPUDesign.(15).cnf.hdb
Finial(20100415)/db/CPUDesign.(16).cnf.cdb
Finial(20100415)/db/CPUDesign.(16).cnf.hdb
Finial(20100415)/db/CPUDesign.(17).cnf.cdb
Finial(20100415)/db/CPUDesign.(17).cnf.hdb
Finial(20100415)/db/CPUDesign.(18).cnf.cdb
Finial(20100415)/db/CPUDesign.(18).cnf.hdb
Finial(20100415)/db/CPUDesign.(19).cnf.cdb
Finial(20100415)/db/CPUDesign.(19).cnf.hdb
Finial(20100415)/db/CPUDesign.(2).cnf.cdb
Finial(20100415)/db/CPUDesign.(2).cnf.hdb
Finial(20100415)/db/CPUDesign.(20).cnf.cdb
Finial(20100415)/db/CPUDesign.(20).cnf.hdb
Finial(20100415)/db/CPUDesign.(21).cnf.cdb
Finial(20100415)/db/CPUDesign.(21).cnf.hdb
Finial(20100415)/db/CPUDesign.(22).cnf.cdb
Finial(20100415)/db/CPUDesign.(22).cnf.hdb
Finial(20100415)/db/CPUDesign.(23).cnf.cdb
Finial(20100415)/db/CPUDesign.(23).cnf.hdb
Finial(20100415)/db/CPUDesign.(24).cnf.cdb
Finial(20100415)/db/CPUDesign.(24).cnf.hdb
Finial(20100415)/db/CPUDesign.(25).cnf.cdb
Finial(20100415)/db/CPUDesign.(25).cnf.hdb
Finial(20100415)/db/CPUDesign.(26).cnf.cdb
Finial(20100415)/db/CPUDesign.(26).cnf.hdb
Finial(20100415)/db/CPUDesign.(3).cnf.cdb
Finial(20100415)/db/CPUDesign.(3).cnf.hdb
Finial(20100415)/db/CPUDesign.(4).cnf.cdb
Finial(20100415)/db/CPUDesign.(4).cnf.hdb
Finial(20100415)/db/CPUDesign.(5).cnf.cdb
Finial(20100415)/db/CPUDesign.(5).cnf.hdb
Finial(20100415)/db/CPUDesign.(6).cnf.cdb
Finial(20100415)/db/CPUDesign.(6).cnf.hdb
Finial(20100415)/db/CPUDesign.(7).cnf.cdb
Finial(20100415)/db/CPUDesign.(7).cnf.hdb
Finial(20100415)/db/CPUDesign.(8).cnf.cdb
Finial(20100415)/db/CPUDesign.(8).cnf.hdb
Finial(20100415)/db/CPUDesign.(9).cnf.cdb
Finial(20100415)/db/CPUDesign.(9).cnf.hdb
Finial(20100415)/db/CPUDesign.asm.qmsg
Finial(20100415)/db/CPUDesign.cbx.xml
Finial(20100415)/db/CPUDesign.cmp.rdb
Finial(20100415)/db/CPUDesign.db_info
Finial(20100415)/db/CPUDesign.eco.cdb
Finial(20100415)/db/CPUDesign.eds_overflow
Finial(20100415)/db/CPUDesign.fit.qmsg
Finial(20100415)/db/CPUDesign.fnsim.cdb
Finial(20100415)/db/CPUDesign.fnsim.hdb
Finial(20100415)/db/CPUDesign.hier_info
Finial(20100415)/db/CPUDesign.hif
Finial(20100415)/db/CPUDesign.map.cdb
Finial(20100415)/db/CPUDesign.map.hdb
Finial(20100415)/db/CPUDesign.map.logdb
Finial(20100415)/db/CPUDesign.map.qmsg
Finial(20100415)/db/CPUDesign.pre_map.cdb
Finial(20100415)/db/CPUDesign.pre_map.hdb
Finial(20100415)/db/CPUDesign.psp
Finial(20100415)/db/CPUDesign.rtlv.hdb
Finial(20100415)/db/CPUDesign.rtlv_sg.cdb
Finial(20100415)/db/CPUDesign.rtlv_sg_swap.cdb
Finial(20100415)/db/CPUDesign.sgdiff.cdb
Finial(20100415)/db/CPUDesign.sgdiff.hdb
Finial(20100415)/db/CPUDesign.sim.hdb
Finial(20100415)/db/CPUDesign.sim.qmsg
Finial(20100415)/db/CPUDesign.sim.rdb
Finial(20100415)

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