lab4/bitinit.log
lab4/clock_generator_0.log
lab4/libgen.log
lab4/platgen.log
lab4/platgen.opt
lab4/system.bsb
lab4/system.log
lab4/system.make
lab4/system.mhs
lab4/system.mss
lab4/system.xmp
lab4/system_incl.make
lab4/_impactbatch.log
lab4/__xps/bitinit.opt
lab4/__xps/libgen.opt
lab4/__xps/platgen.opt
lab4/__xps/simgen.opt
lab4/__xps/system.gui
lab4/__xps/system_routed
lab4/__xps/testapp_memory_compiler.opt
lab4/__xps/vpgen.opt
lab4/__xps/xplorer.opt
lab4/__xps/xpsxflow.opt
lab4/__xps/.dswkshop/ds_Report.css
lab4/__xps/.dswkshop/ds_Report.js
lab4/__xps/.dswkshop/IMG_closeBranch.gif
lab4/__xps/.dswkshop/IMG_LicensedCore.bmp
lab4/__xps/.dswkshop/IMG_openBranch.gif
lab4/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.css
lab4/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl
lab4/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl
lab4/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl
lab4/__xps/.dswkshop/MdtXdsGen_HTMLPeripherals.xsl
lab4/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlkDBifDefs.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlkDBusLaneSpaces.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlkdBusses.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlkDCalculations.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlkDDimensions.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlkdIOPorts.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlkDModuleDefs.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlkDPeripherals.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlkdProcessors.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_BlockDiagram.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_Colors.xsl
lab4/__xps/.dswkshop/MdtXdsSVG_Render.css
lab4/__xps/.dswkshop/svg10.dtd
lab4/TestApp_Memory/executable.elf
lab4/TestApp_Memory/TestApp_Memory_linker_script.ld
lab4/TestApp_Memory/TestApp_Memory_linker_script.ld.bak
lab4/TestApp_Memory/src/lab4.c
lab4/TestApp_Memory/src/TestApp_Memory_LinkScr.ld
lab4/synthesis/clock_generator_0_wrapper.lso
lab4/synthesis/clock_generator_0_wrapper_xst.prj
lab4/synthesis/clock_generator_0_wrapper_xst.scr
lab4/synthesis/clock_generator_0_wrapper_xst.srp
lab4/synthesis/debug_module_wrapper.lso
lab4/synthesis/debug_module_wrapper_xst.prj
lab4/synthesis/debug_module_wrapper_xst.scr
lab4/synthesis/debug_module_wrapper_xst.srp
lab4/synthesis/dlmb_cntlr_wrapper.lso
lab4/synthesis/dlmb_cntlr_wrapper_xst.prj
lab4/synthesis/dlmb_cntlr_wrapper_xst.scr
lab4/synthesis/dlmb_cntlr_wrapper_xst.srp
lab4/synthesis/dlmb_wrapper.lso
lab4/synthesis/dlmb_wrapper_xst.prj
lab4/synthesis/dlmb_wrapper_xst.scr
lab4/synthesis/dlmb_wrapper_xst.srp
lab4/synthesis/ilmb_cntlr_wrapper.lso
lab4/synthesis/ilmb_cntlr_wrapper_xst.prj
lab4/synthesis/ilmb_cntlr_wrapper_xst.scr
lab4/synthesis/ilmb_cntlr_wrapper_xst.srp
lab4/synthesis/ilmb_wrapper.lso
lab4/synthesis/ilmb_wrapper_xst.prj
lab4/synthesis/ilmb_wrapper_xst.scr
lab4/synthesis/ilmb_wrapper_xst.srp
lab4/synthesis/leds_8bit_wrapper.lso
lab4/synthesis/leds_8bit_wrapper_xst.prj
lab4/synthesis/leds_8bit_wrapper_xst.scr
lab4/synthesis/leds_8bit_wrapper_xst.srp
lab4/synthesis/lmb_bram_wrapper.lso
lab4/synthesis/lmb_bram_wrapper_xst.prj
lab4/synthesis/lmb_bram_wrapper_xst.scr
lab4/synthesis/lmb_bram_wrapper_xst.srp
lab4/synthesis/mb_plb_wrapper.lso
lab4/synthesis/mb_plb_wrapper_xst.prj
lab4/synthesis/mb_plb_wrapper_xst.scr
lab4/synthesis/mb_plb_wrapper_xst.srp
lab4/synthesis/microblaze_0_wrapper.lso
lab4/synthesis/microblaze_0_wrapper_xst.prj
lab4/synthesis/microblaze_0_wrapper_xst.scr
lab4/synthesis/microblaze_0_wrapper_xst.srp
lab4/synthesis/micron_ram_util_bus_split_1_wrapper.lso
lab4/synthesis/micron_ram_util_bus_split_1_wrapper_xst.prj
lab4/synthesis/micron_ram_util_bus_split_1_wrapper_xst.scr
lab4/synthesis/micron_ram_util_bus_split_1_wrapper_xst.srp
lab4/synthesis/micron_ram_wrapper.lso
lab4/synthesis/micron_ram_wrapper_xst.prj
lab4/synthesis/micron_ram_wrapper_xst.scr
lab4/synthesis/micron_ram_wrapper_xst.srp
lab4/synthesis/proc_sys_reset_0_wrapper.lso
lab4/synthesis/proc_sys_reset_0_wrapper_xst.prj
lab4/synthesis/proc_sys_reset_0_wrapper_xst.scr
lab4/synthesis/proc_sys_reset_0_wrapper_xst.srp
lab4/synthesis/rs232_port_wrapper.lso
lab4/synthesis/rs232_port_wrapper_xst.prj
lab4/synthesis/rs232_port_wrapper_xst.scr
lab4/synthesis/rs232_port_wrapper_xst.srp
lab4/synthesis/switchs_ip_0_wrapper.lso
lab4/synthesis/switchs_ip_0_wrapper_xst.prj
lab4/synthesis/switchs_ip_0_wrapper_xst.scr
lab4/synthesis/switchs_ip_0_wrapper_xst.srp
lab4/synthesis/synthesis.sh
lab4/synthesis/system.lso
lab4/synthesis/system_xst.prj
lab4/synthesis/system_xst.scr
lab4/synthesis/system_xst.srp
lab4/synthesis/xlnx_auto_0.ise
lab4/synthesis/xps_bram_if_cntlr_0_wrapper.lso
lab4/synthesis/xps_bram_if_cntlr_0_wrapper_xst.prj
lab4/synthesis/xps_bram_if_cntlr_0_wrapper_xst.scr
lab4/synthesis/xps_bram_if_cntlr_0_wrapper_xst.srp
lab4/synthesis/xps_bram_wrapper.lso
lab4/synthesis/xps_bram_wrapper_xst.prj
lab4/synthesis/xps_bram_wrapper_xst.scr
lab4/synthesis/xps_bram_wrapper_xst.srp
lab4/synthesis/xlnx_auto_0_xdb/tmp/ise.lock
lab4/synthesis/xlnx_auto_0_xdb/tmp/ise/version
lab4/synthesis/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
lab4/synthesis/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/STE/regkeys
lab4/synthesis/xlnx_auto_0_xd