- viterbi This a code generator for some kinds of decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.
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- Academic-result-management-system It s academic result management system documentation. The academic result management system project aims at performing calculations of results
- result calibration
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文件名称:map
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MAP algoritm coding and decoding Turbo trelis sistems of codec use small interliver and 11 simbols
相关搜索： turbo map
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下载文件列表
f_smb_bits.m
mode101.m
sv_map.m
TUR_F.m
f_dint.m
mode101.m
sv_map.m
TUR_F.m
f_dint.m
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