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文件名称:digi_clock

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.99mb
  • 已下载：
    0次
  • 提 供 者：
    jian****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
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用verilog写的数字钟程序，已在altera公司的cyclone IV开发板上运行成功，很有价值-Digital clock using verilog written procedures for the company in altera cyclone IV development board to run a successful, valuable
(系统自动生成,下载前可以参看下载内容)

下载文件列表

digi_clock/db/digi_clock.(0).cnf.cdb
digi_clock/db/digi_clock.(0).cnf.hdb
digi_clock/db/digi_clock.(1).cnf.cdb
digi_clock/db/digi_clock.(1).cnf.hdb
digi_clock/db/digi_clock.(2).cnf.cdb
digi_clock/db/digi_clock.(2).cnf.hdb
digi_clock/db/digi_clock.(3).cnf.cdb
digi_clock/db/digi_clock.(3).cnf.hdb
digi_clock/db/digi_clock.(4).cnf.cdb
digi_clock/db/digi_clock.(4).cnf.hdb
digi_clock/db/digi_clock.(5).cnf.cdb
digi_clock/db/digi_clock.(5).cnf.hdb
digi_clock/db/digi_clock.amm.cdb
digi_clock/db/digi_clock.asm.qmsg
digi_clock/db/digi_clock.asm.rdb
digi_clock/db/digi_clock.atom_map.rvd
digi_clock/db/digi_clock.cbx.xml
digi_clock/db/digi_clock.cmp.bpm
digi_clock/db/digi_clock.cmp.cdb
digi_clock/db/digi_clock.cmp.hdb
digi_clock/db/digi_clock.cmp.kpt
digi_clock/db/digi_clock.cmp.logdb
digi_clock/db/digi_clock.cmp.rdb
digi_clock/db/digi_clock.cmp_merge.kpt
digi_clock/db/digi_clock.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
digi_clock/db/digi_clock.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
digi_clock/db/digi_clock.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
digi_clock/db/digi_clock.db_info
digi_clock/db/digi_clock.eda.qmsg
digi_clock/db/digi_clock.fit.qmsg
digi_clock/db/digi_clock.hier_info
digi_clock/db/digi_clock.hif
digi_clock/db/digi_clock.idb.cdb
digi_clock/db/digi_clock.lpc.html
digi_clock/db/digi_clock.lpc.rdb
digi_clock/db/digi_clock.lpc.txt
digi_clock/db/digi_clock.map.bpm
digi_clock/db/digi_clock.map.cdb
digi_clock/db/digi_clock.map.hdb
digi_clock/db/digi_clock.map.kpt
digi_clock/db/digi_clock.map.logdb
digi_clock/db/digi_clock.map.qmsg
digi_clock/db/digi_clock.map_bb.cdb
digi_clock/db/digi_clock.map_bb.hdb
digi_clock/db/digi_clock.map_bb.logdb
digi_clock/db/digi_clock.pre_map.cdb
digi_clock/db/digi_clock.pre_map.hdb
digi_clock/db/digi_clock.rpp.qmsg
digi_clock/db/digi_clock.rtlv.hdb
digi_clock/db/digi_clock.rtlv_sg.cdb
digi_clock/db/digi_clock.rtlv_sg_swap.cdb
digi_clock/db/digi_clock.sgate.rvd
digi_clock/db/digi_clock.sgate_sm.rvd
digi_clock/db/digi_clock.sgdiff.cdb
digi_clock/db/digi_clock.sgdiff.hdb
digi_clock/db/digi_clock.sld_design_entry.sci
digi_clock/db/digi_clock.sld_design_entry_dsc.sci
digi_clock/db/digi_clock.smart_action.txt
digi_clock/db/digi_clock.sta.qmsg
digi_clock/db/digi_clock.sta.rdb
digi_clock/db/digi_clock.syn_hier_info
digi_clock/db/digi_clock.tiscmp.slow_1200mv_85c.ddb
digi_clock/db/digi_clock.tis_db_list.ddb
digi_clock/db/digi_clock.tmw_info
digi_clock/db/logic_util_heursitic.dat
digi_clock/db/prev_cmp_digi_clock.qmsg
digi_clock/digi_clock.asm.rpt
digi_clock/digi_clock.done
digi_clock/digi_clock.dpf
digi_clock/digi_clock.eda.rpt
digi_clock/digi_clock.fit.rpt
digi_clock/digi_clock.fit.smsg
digi_clock/digi_clock.fit.summary
digi_clock/digi_clock.flow.rpt
digi_clock/digi_clock.map.rpt
digi_clock/digi_clock.map.smsg
digi_clock/digi_clock.map.summary
digi_clock/digi_clock.pin
digi_clock/digi_clock.qpf
digi_clock/digi_clock.qsf
digi_clock/digi_clock.sof
digi_clock/digi_clock.sta.rpt
digi_clock/digi_clock.sta.summary
digi_clock/digi_clock.txt
digi_clock/digi_clock.v
digi_clock/digi_clock.v.bak
digi_clock/digi_clock_nativelink_simulation.rpt
digi_clock/incremental_db/compiled_partitions/digi_clock.db_info
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.cmp.cbp
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.cmp.cdb
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.cmp.dfp
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.cmp.hdb
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.cmp.kpt
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.cmp.logdb
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.cmp.rcfdb
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.cmp.re.rcfdb
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.map.cbp
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.map.cdb
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.map.dpi
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.map.hdb
digi_clock/incremental_db/compiled_partitions/digi_clock.root_partition.map.kpt
digi_clock/incremental_db/README
digi_clock/simulation/modelsim/digi_clock.sft
digi_clock/simulation/modelsim/digi_clock.vo
digi_clock/simulation/modelsim/digi_clock_7_1200mv_0c_slow.vo
digi_clock/simulation/modelsim/digi_clock_7_1200mv_0c_v_slow.sdo
digi_clock/simulation/modelsim/digi_clock_7_1200mv_85c_slow.vo
digi_clock/simulation/modelsim/digi_clock_7_1200mv_85c_v_slow.sdo
digi_clock/simulation/modelsim/digi_clock_min_1200mv_0c_fast.vo
digi_clock/simulation/modelsim/digi_clock_min_1200mv_0c_v_fast.sdo
digi_clock/simulation/modelsim/digi_clock_modelsim.xrf
digi_clock/simulation/modelsim/digi_clock_run_msim_rtl_verilog.do
digi_clock/simulation/modelsim/digi_clock_v.sdo
digi_clock/simulation/modelsim/modelsim.ini
digi_clock/simulation/modelsim/msim_transcript
digi_clock/simulation/modelsim/rtl_work/clock/verilog.prw
digi_clock/simulation/modelsim/rtl_work/cl

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