uart/UART设计文档.pdf
uart/创造力电子开发网.url
uart/读我.txt
uart/创造力电子开发网/注册-创造力电子开发网.url
uart/创造力电子开发网/登录-创造力电子开发网.url
uart/创造力电子开发网/首页-创造力电子开发网.url
uart/Mcu/UartTest/FpgaInc.h
uart/Mcu/UartTest/main.c
uart/Mcu/UartTest/stdinc.h
uart/Mcu/UartTest/UartCtrl.c
uart/Mcu/UartTest/UartCtrl.h
uart/Mcu/UartTest/UartTest.dep
uart/Mcu/UartTest/UartTest.ewd
uart/Mcu/UartTest/UartTest.ewp
uart/Mcu/UartTest/UartTest.eww
uart/Mcu/UartTest/settings/test.cspy.bat
uart/Mcu/UartTest/settings/test.dbgdt
uart/Mcu/UartTest/settings/test.dni
uart/Mcu/UartTest/settings/test.wsdt
uart/Mcu/UartTest/settings/UartTest.cspy.bat
uart/Mcu/UartTest/settings/UartTest.dni
uart/Mcu/UartTest/settings/UartTest.wsdt
uart/fpga/V0p10/top.bsf
uart/fpga/V0p10/uart.asm.rpt
uart/fpga/V0p10/uart.cdf
uart/fpga/V0p10/uart.done
uart/fpga/V0p10/uart.dpf
uart/fpga/V0p10/uart.eda.rpt
uart/fpga/V0p10/uart.fit.rpt
uart/fpga/V0p10/uart.fit.smsg
uart/fpga/V0p10/uart.fit.summary
uart/fpga/V0p10/uart.flow.rpt
uart/fpga/V0p10/uart.map.rpt
uart/fpga/V0p10/uart.map.smsg
uart/fpga/V0p10/uart.map.summary
uart/fpga/V0p10/uart.pin
uart/fpga/V0p10/uart.pof
uart/fpga/V0p10/uart.qpf
uart/fpga/V0p10/uart.qsf
uart/fpga/V0p10/uart.qws
uart/fpga/V0p10/uart.sof
uart/fpga/V0p10/uart.tan.rpt
uart/fpga/V0p10/uart.tan.summary
uart/fpga/V0p10/uart_assignment_defaults.qdf
uart/fpga/V0p10/uart_description.txt
uart/fpga/V0p10/uart_nativelink_simulation.rpt
uart/fpga/V0p10/testbench/ModelSim.jpg
uart/fpga/V0p10/testbench/tcl_stacktrace.txt
uart/fpga/V0p10/testbench/top_tb.v
uart/fpga/V0p10/testbench/transcript
uart/fpga/V0p10/testbench/uart.cr.mti
uart/fpga/V0p10/testbench/uart.mpf
uart/fpga/V0p10/testbench/vish_stacktrace.vstf
uart/fpga/V0p10/testbench/vsim.wlf
uart/fpga/V0p10/testbench/vsim_stacktrace.vstf
uart/fpga/V0p10/testbench/work/_info
uart/fpga/V0p10/testbench/work/uart/verilog.asm
uart/fpga/V0p10/testbench/work/uart/_primary.dat
uart/fpga/V0p10/testbench/work/uart/_primary.vhd
uart/fpga/V0p10/testbench/work/txd/verilog.asm
uart/fpga/V0p10/testbench/work/txd/_primary.dat
uart/fpga/V0p10/testbench/work/txd/_primary.vhd
uart/fpga/V0p10/testbench/work/top_tb/verilog.asm
uart/fpga/V0p10/testbench/work/top_tb/_primary.dat
uart/fpga/V0p10/testbench/work/top_tb/_primary.vhd
uart/fpga/V0p10/testbench/work/top/verilog.asm
uart/fpga/V0p10/testbench/work/top/_primary.dat
uart/fpga/V0p10/testbench/work/top/_primary.vhd
uart/fpga/V0p10/testbench/work/rxd/verilog.asm
uart/fpga/V0p10/testbench/work/rxd/_primary.dat
uart/fpga/V0p10/testbench/work/rxd/_primary.vhd
uart/fpga/V0p10/testbench/work/ebi/verilog.asm
uart/fpga/V0p10/testbench/work/ebi/_primary.dat
uart/fpga/V0p10/testbench/work/ebi/_primary.vhd
uart/fpga/V0p10/testbench/work/division/verilog.asm
uart/fpga/V0p10/testbench/work/division/_primary.dat
uart/fpga/V0p10/testbench/work/division/_primary.vhd
uart/fpga/V0p10/testbench/work/divider/verilog.asm
uart/fpga/V0p10/testbench/work/divider/_primary.dat
uart/fpga/V0p10/testbench/work/divider/_primary.vhd
uart/fpga/V0p10/testbench/cycloneII_v/_info
uart/fpga/V0p10/src/divider.v
uart/fpga/V0p10/src/ebi.v
uart/fpga/V0p10/src/rxd.v
uart/fpga/V0p10/src/top.v
uart/fpga/V0p10/src/txd.v
uart/fpga/V0p10/src/uart.v
uart/fpga/V0p10/simulation/modelsim/modelsim.ini
uart/fpga/V0p10/simulation/modelsim/msim_transcript
uart/fpga/V0p10/simulation/modelsim/uart.sft
uart/fpga/V0p10/simulation/modelsim/uart.vo
uart/fpga/V0p10/simulation/modelsim/uart_modelsim.xrf
uart/fpga/V0p10/simulation/modelsim/uart_run_msim_rtl_verilog.do
uart/fpga/V0p10/simulation/modelsim/uart_run_msim_rtl_verilog.do.bak
uart/fpga/V0p10/simulation/modelsim/uart_v.sdo
uart/fpga/V0p10/simulation/modelsim/vsim.wlf
uart/fpga/V0p10/simulation/modelsim/rtl_work/_info
uart/fpga/V0p10/simulation/modelsim/rtl_work/_vmake
uart/fpga/V0p10/simulation/modelsim/rtl_work/uart/verilog.prw
uart/fpga/V0p10/simulation/modelsim/rtl_work/uart/verilog.psm
uart/fpga/V0p10/simulation/modelsim/rtl_work/uart/_primary.dat
uart/fpga/V0p10/simulation/modelsim/rtl_work/uart/_primary.dbs
uart/fpga/V0p10/simulation/modelsim/rtl_work/uart/_primary.vhd
uart/fpga/V0p10/simulation/modelsim/rtl_work/txd/verilog.prw
uart/fpga/V0p10/simulation/modelsim/rtl_work/txd/verilog.psm
uart/fpga/V0p10/simulation/modelsim/rtl_work/txd/_primary.dat
uart/fpga/V0p10/simulation/modelsim/rtl_work/txd/_primary.dbs
uart/fpga/V0p10/simulation/modelsim/rtl_work/txd/_primary.vhd
uart/fpga/V0p10/simulation/modelsim/rtl_work/top_tb/verilog.prw
uart/fpga/V0p10/simulation/modelsim/rtl_work/top_tb/verilog.psm
uart/fpga/V0p10/simulation/modelsim/rtl_work/top_tb/_primary.dat
uart/fpga/V0p10/simulation/modelsim/rtl_work/top_tb/_primary.dbs
uart/fpga/V0p10/simulation/modelsim/rtl_work/top_tb/_primary.vhd
uart/fpga/V0p10/simulation/modelsim/rtl_work/top/verilog.prw
uart/fpga/V0p10/simulation/modelsim/rtl_work/top/verilog.psm
uart/fpga/V0p10/simulation/modelsim/rtl_work/top/_primary.dat
uart/fpga/V0p10/simulation/modelsim/rtl_work/top/_primary.dbs
uart/fpga/V0p10/simulation/modelsim/rtl_work/top/_primary.vhd
uart/fpga/V0p10/simulation/modelsim/rtl_work/rxd/verilog.prw
uart/fpga/V0p10/simulation/modelsim/rtl_work/rxd/verilog.psm