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文件名称:UART_Quartus_verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.72mb
  • 已下载：
    1次
  • 提 供 者：
    杰**
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用Verilog编写的异步串口通信程序，开发环境为Quartus II，具有一定的参考价值。-Written in Verilog asynchronous serial communication program development environment for the Quartus II, with some reference value.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

UART_Quartus_verilog/db/txmit.(0).cnf.cdb
UART_Quartus_verilog/db/txmit.(0).cnf.hdb
UART_Quartus_verilog/db/txmit.asm.qmsg
UART_Quartus_verilog/db/txmit.cbx.xml
UART_Quartus_verilog/db/txmit.cmp.cdb
UART_Quartus_verilog/db/txmit.cmp.hdb
UART_Quartus_verilog/db/txmit.cmp.kpt
UART_Quartus_verilog/db/txmit.cmp.logdb
UART_Quartus_verilog/db/txmit.cmp.rdb
UART_Quartus_verilog/db/txmit.cmp.tdb
UART_Quartus_verilog/db/txmit.cmp0.ddb
UART_Quartus_verilog/db/txmit.dbp
UART_Quartus_verilog/db/txmit.db_info
UART_Quartus_verilog/db/txmit.eco.cdb
UART_Quartus_verilog/db/txmit.eda.qmsg
UART_Quartus_verilog/db/txmit.fit.qmsg
UART_Quartus_verilog/db/txmit.hier_info
UART_Quartus_verilog/db/txmit.hif
UART_Quartus_verilog/db/txmit.map.cdb
UART_Quartus_verilog/db/txmit.map.hdb
UART_Quartus_verilog/db/txmit.map.logdb
UART_Quartus_verilog/db/txmit.map.qmsg
UART_Quartus_verilog/db/txmit.pre_map.cdb
UART_Quartus_verilog/db/txmit.pre_map.hdb
UART_Quartus_verilog/db/txmit.psp
UART_Quartus_verilog/db/txmit.rtlv.hdb
UART_Quartus_verilog/db/txmit.rtlv_sg.cdb
UART_Quartus_verilog/db/txmit.rtlv_sg_swap.cdb
UART_Quartus_verilog/db/txmit.sgdiff.cdb
UART_Quartus_verilog/db/txmit.sgdiff.hdb
UART_Quartus_verilog/db/txmit.signalprobe.cdb
UART_Quartus_verilog/db/txmit.sld_design_entry.sci
UART_Quartus_verilog/db/txmit.sld_design_entry_dsc.sci
UART_Quartus_verilog/db/txmit.syn_hier_info
UART_Quartus_verilog/db/txmit.tan.qmsg
UART_Quartus_verilog/simulation/modelsim/220model.v
UART_Quartus_verilog/simulation/modelsim/altera_mf.v
UART_Quartus_verilog/simulation/modelsim/cyclone_atoms.v
UART_Quartus_verilog/simulation/modelsim/transcript
UART_Quartus_verilog/simulation/modelsim/txmit.vo
UART_Quartus_verilog/simulation/modelsim/txmit_modelsim.xrf
UART_Quartus_verilog/simulation/modelsim/txmit_tb.v
UART_Quartus_verilog/simulation/modelsim/txmit_v.sdo
UART_Quartus_verilog/simulation/modelsim/vsim.wlf
UART_Quartus_verilog/simulation/modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@l@p@m_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@l@p@m_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@l@p@m_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@m@f_pll_reg/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@m@f_pll_reg/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@m@f_pll_reg/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@m@f_ram7x20_syn/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@m@f_ram7x20_syn/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@m@f_ram7x20_syn/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@m@f_stratixii_pll/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@m@f_stratixii_pll/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@m@f_stratixii_pll/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/@m@f_stratix_pll/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/@m@f_stratix_pll/_primary.dat
UART_Quartus_verilog/simulation/modelsim/work/@m@f_stratix_pll/_primary.vhd
UART_Quartus_verilog/simulation/modelsim/work/alt3pram/verilog.asm
UART_Quartus_verilog/simulation/modelsim/work/alt3pram/_primary.dat
UART_Quartus_verilog/simulation/modelsim/

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