Intel从386开始，在调试方面引入了调试寄存器和硬件断点的概念。

IA-32处理器定义了8个调试寄存器，分别为DR0~DR7。在32位模式下，它们都是32位的；在64位模式下，都是64位。

DR4和DR5是保留的。其他6个寄存器为：4个32位的调试地址寄存器（DR0~DR3）；1个32位的调试控制寄存器（DR7）和1个32位的调试状态寄存器（DR6）。通过以上寄存器可以最多设置4个断点，DR0~DR3用来指定断点的内存（线性地址）或I/O地址。DR7用来进一步定义断点的中断条件。DR6的作用是当调试事件发生时，向调试器（debugger）报告事件的详细信息，以供调试器判断发生的是何种事件。-Intel started from 386, introduced in debugging hardware debug breakpoint registers and the concept.

　　 IA-32 processor defines eight debug registers, respectively, DR0 ~ DR7. In 32-bit mode, they are 32　in 64-bit mode, all 64-bit.

　　 DR4 and DR5 are reserved. The other six registers are: four 32-bit debug address register (DR0 ~ DR3)　1 32-bit debug control register (DR7) and a 32-bit debug status register (DR6). Through the above register can set up to four breakpoints, DR0 ~ DR3 is used to specify the memory breakpoint (linear address) or I/O address. DR7 is used to further define the breakpoint interrupt condition. The role of DR6 when debugging event occurs, the debugger (debugger) reported details of the event for the debugger to determine what kind of events took place.