用verilog语言编写的帧同步搜索电路，输入数据data为8 bit并行数据流，基本结构为数据帧，帧长为10字节，帧同步字为H“FF”。clk为输入同步时钟。-Verilog language for　frame synchronous search circuit, the input data is data for the 8-bit parallel data stream, the basic structure of the data frame, the frame length of 10 bytes, the frame synchronization word H "FF". clk to input sync clock.