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文件名称:verilog-ip-core

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-11-16
  • 文件大小：
    3.62mb
  • 已下载：
    0次
  • 提 供 者：
    刘***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

verilog ip核，源代码，ethernet，

video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
(系统自动生成,下载前可以参看下载内容)

下载文件列表

verilog ip core/ac97/ac97_ctrl/bench/CVS/Entries
verilog ip core/ac97/ac97_ctrl/bench/CVS/Repository
verilog ip core/ac97/ac97_ctrl/bench/CVS/Root
verilog ip core/ac97/ac97_ctrl/bench/verilog/ac97_codec_sin.v
verilog ip core/ac97/ac97_ctrl/bench/verilog/ac97_codec_sout.v
verilog ip core/ac97/ac97_ctrl/bench/verilog/ac97_codec_top.v
verilog ip core/ac97/ac97_ctrl/bench/verilog/CVS/Entries
verilog ip core/ac97/ac97_ctrl/bench/verilog/CVS/Repository
verilog ip core/ac97/ac97_ctrl/bench/verilog/CVS/Root
verilog ip core/ac97/ac97_ctrl/bench/verilog/tests.v
verilog ip core/ac97/ac97_ctrl/bench/verilog/test_bench_top.v
verilog ip core/ac97/ac97_ctrl/bench/verilog/wb_mast_model.v
verilog ip core/ac97/ac97_ctrl/bench/verilog/wb_model_defines.v
verilog ip core/ac97/ac97_ctrl/CVS/Entries
verilog ip core/ac97/ac97_ctrl/CVS/Repository
verilog ip core/ac97/ac97_ctrl/CVS/Root
verilog ip core/ac97/ac97_ctrl/doc/ac97_doc.pdf
verilog ip core/ac97/ac97_ctrl/doc/CVS/Entries
verilog ip core/ac97/ac97_ctrl/doc/CVS/Repository
verilog ip core/ac97/ac97_ctrl/doc/CVS/Root
verilog ip core/ac97/ac97_ctrl/doc/README.txt
verilog ip core/ac97/ac97_ctrl/doc/STATUS.txt
verilog ip core/ac97/ac97_ctrl/rtl/CVS/Entries
verilog ip core/ac97/ac97_ctrl/rtl/CVS/Repository
verilog ip core/ac97/ac97_ctrl/rtl/CVS/Root
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_cra.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_defines.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_dma_if.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_dma_req.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_fifo_ctrl.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_int.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_in_fifo.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_out_fifo.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_prc.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_rf.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_rst.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_sin.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_soc.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_sout.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_top.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/ac97_wb_if.v
verilog ip core/ac97/ac97_ctrl/rtl/verilog/CVS/Entries
verilog ip core/ac97/ac97_ctrl/rtl/verilog/CVS/Repository
verilog ip core/ac97/ac97_ctrl/rtl/verilog/CVS/Root
verilog ip core/ac97/ac97_ctrl/sim/CVS/Entries
verilog ip core/ac97/ac97_ctrl/sim/CVS/Repository
verilog ip core/ac97/ac97_ctrl/sim/CVS/Root
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/bin/CVS/Entries
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/bin/CVS/Repository
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/bin/CVS/Root
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/bin/Makefile
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/CVS/Entries
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/CVS/Repository
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/CVS/Root
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/run/CVS/Entries
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/run/CVS/Repository
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/run/CVS/Root
verilog ip core/ac97/ac97_ctrl/sim/rtl_sim/run/Makefile
verilog ip core/ac97/ac97_ctrl/syn/bin/comp.dc
verilog ip core/ac97/ac97_ctrl/syn/bin/CVS/Entries
verilog ip core/ac97/ac97_ctrl/syn/bin/CVS/Repository
verilog ip core/ac97/ac97_ctrl/syn/bin/CVS/Root
verilog ip core/ac97/ac97_ctrl/syn/bin/design_spec.dc
verilog ip core/ac97/ac97_ctrl/syn/bin/lib_spec.dc
verilog ip core/ac97/ac97_ctrl/syn/bin/read.dc
verilog ip core/ac97/ac97_ctrl/syn/CVS/Entries
verilog ip core/ac97/ac97_ctrl/syn/CVS/Repository
verilog ip core/ac97/ac97_ctrl/syn/CVS/Root
verilog ip core/ac97/ac97_ctrl/syn/log/CVS/Entries
verilog ip core/ac97/ac97_ctrl/syn/log/CVS/Repository
verilog ip core/ac97/ac97_ctrl/syn/log/CVS/Root
verilog ip core/ac97/ac97_ctrl/syn/out/CVS/Entries
verilog ip core/ac97/ac97_ctrl/syn/out/CVS/Repository
verilog ip core/ac97/ac97_ctrl/syn/out/CVS/Root
verilog ip core/ac97/ac97_ctrl/syn/run/CVS/Entries
verilog ip core/ac97/ac97_ctrl/syn/run/CVS/Repository
verilog ip core/ac97/ac97_ctrl/syn/run/CVS/Root
verilog ip core/ac97/ac97_ctrl.tar.gz
verilog ip core/ac97/ac97_doc.pdf
verilog ip core/ethernet/ethernet/bench/CVS/Entries
verilog ip core/ethernet/ethernet/bench/CVS/Repository
verilog ip core/ethernet/ethernet/bench/CVS/Root
verilog ip core/ethernet/ethernet/bench/verilog/CVS/Entries
verilog ip core/ethernet/ethernet/bench/verilog/CVS/Repository
verilog ip core/ethernet/ethernet/bench/verilog/CVS/Root
verilog ip core/ethernet/ethernet/bench/verilog/eth_host.v
verilog ip core/ethernet/ethernet/bench/verilog/eth_memory.v
verilog ip core/ethernet/ethernet/bench/verilog/eth_phy.v
verilog ip core/ethernet/ethernet/bench/verilog/eth_phy_defines.v
verilog ip core/ethernet/ethernet/bench/verilog/tb_cop.v
verilog ip core/ethernet/ethernet/bench/verilog/tb_ethernet.v
verilog ip core/ethernet/ethernet/bench/verilog/tb_ethernet_with_cop.v
verilog ip core/ethernet/ethernet/bench/verilog/tb_eth_defines.v
verilog ip core/ethernet/ethernet/bench/verilog/tb_eth_top.v
verilog ip core/ethernet/ethernet/bench/verilog/wb_bus_mon.v
verilog ip cor

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