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文件名称:Full-Adder
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- 上传时间：2012-11-16
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文件大小：1.21kb
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用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
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下载文件列表
test_Full_Adder_1.vhd
Full_Adder_1.vhd
Full_Adder_1.vhd
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