This VHDL or Verilog source code is intended as a design reference

// which illustrates how these types of functions can be implemented.

// It is the user s responsibility to verify their design for

// consistency and functionality through the use of formal

// verification methods. Lattice Semiconductor provides no warranty

// regarding the use or functionality of this code.- This VHDL or Verilog source code is intended as a design reference

//　 which illustrates how these types of functions can be implemented.

//　 It is the user s responsibility to verify their design for

//　 consistency and functionality through the use of formal

//　 verification methods.　Lattice Semiconductor provides no warranty

//　 regarding the use or functionality of this code.